公开(公告)号：US20230317469A1

公开(公告)日：2023-10-05

申请号：US17711885

申请日：2022-04-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Bor Chiuan Hsieh ,  Po-Hsien Cheng ,  Tsai-Jung Ho ,  Po-Cheng Shih ,  Jr-Hung Li ,  Tze-Liang Lee

IPC: H01L21/311 ,  H01L21/768 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L21/31144 ,  H01L21/76802 ,  H01L29/66795 ,  H01L29/6653 ,  H01L29/456 ,  H01L29/785 ,  H01L21/76831 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/76897

Abstract: A method of forming a semiconductor device includes forming a source/drain region over a substrate; forming a first interlayer dielectric over the source/drain region; forming a gate structure over the substrate and laterally adjacent to the source/drain region; and forming a gate mask over the gate structure, the forming the gate mask comprising: etching a portion of the gate structure to form a recess relative to a top surface of the first interlayer dielectric; depositing a first dielectric layer over the gate structure in the recess and over the first interlayer dielectric; etching a portion of the first dielectric layer; depositing a semiconductor layer over the first dielectric layer in the recess; and planarizing the semiconductor layer to be coplanar with the first interlayer dielectric. In another embodiment, the method further includes forming a gate spacer over the substrate, wherein the etching the portion of the gate structure further comprises etching a portion of the gate spacer.

公开(公告)号：US20220246473A1

公开(公告)日：2022-08-04

申请号：US17524830

申请日：2021-11-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jian-Hong Lu ,  Tsai-Jung Ho ,  Bor Chiuan Hsieh ,  Po-Cheng Shih ,  Tze-Liang Lee

IPC: H01L21/768 ,  H01L29/66 ,  H01L29/40 ,  H01L21/8234

Abstract: A method of forming a semiconductor device includes: forming a fin protruding above a substrate; forming a metal gate over the fin, the metal gate being surround by a dielectric layer; etching the metal gate to reduce a height of the metal gate, where after the etching, a recess is formed over the metal gate between gate spacers of the metal gate; lining sidewalls and a bottom of the recess with a semiconductor material; filling the recess by forming a dielectric material over the semiconductor material; forming a mask layer over the metal gate, where a first opening of the mask layer is directly over a portion of the dielectric layer adjacent to the metal gate; removing the portion of the dielectric layer to form a second opening in the dielectric layer, the second opening exposing an underlying source/drain region; and filling the second opening with a conductive material.

公开(公告)号：US11374127B2

公开(公告)日：2022-06-28

申请号：US16939199

申请日：2020-07-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yao-Jen Chang ,  Chih-Chien Chi ,  Chen-Yuan Kao ,  Hung-Wen Su ,  Kai-Shiang Kuo ,  Po-Cheng Shih ,  Jun-Yi Ruan

IPC: H01L21/00 ,  H01L29/78 ,  H01L29/66 ,  H01L23/522 ,  H01L23/528 ,  H01L21/768 ,  H01L23/532 ,  H01L21/8238 ,  H01L27/092

Abstract: A device, structure, and method are provided whereby an insert layer is utilized to provide additional support for weaker and softer dielectric layer. The insert layer may be applied between two weaker dielectric layers or the insert layer may be used with a single layer of dielectric material. Once formed, trenches and vias are formed within the composite layers, and the insert layer will help to provide support that will limit or eliminate undesired bending or other structural motions that could hamper subsequent process steps, such as filling the trenches and vias with conductive material.

公开(公告)号：US11328952B2

公开(公告)日：2022-05-10

申请号：US17099263

申请日：2020-11-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Cheng Chou ,  Chih-Chien Chi ,  Chung-Chi Ko ,  Yao-Jen Chang ,  Chen-Yuan Kao ,  Kai-Shiang Kuo ,  Po-Cheng Shih ,  Tze-Liang Lee ,  Jun-Yi Ruan

IPC: H01L21/768 ,  H01L21/8234 ,  H01L23/532 ,  H01L21/84 ,  H01L29/66 ,  H01L23/522 ,  H01L23/528 ,  H01L29/78 ,  H01L29/08

Abstract: A device, structure, and method are provided whereby an insert layer is utilized to provide additional support for surrounding dielectric layers. The insert layer may be applied between two dielectric layers. Once formed, trenches and vias are formed within the composite layers, and the insert layer will help to provide support that will limit or eliminate undesired bending or other structural motions that could hamper subsequent process steps, such as filling the trenches and vias with conductive material.

公开(公告)号：US20210057340A1

公开(公告)日：2021-02-25

申请号：US17077556

申请日：2020-10-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chao-Chun Wang ,  Chung-Chi Ko ,  Po-Cheng Shih

IPC: H01L23/528 ,  H01L21/768 ,  H01L23/532 ,  H01L23/522

Abstract: An integrated circuit structure includes a first low-k dielectric layer having a first k value, and a second low-k dielectric layer having a second k value lower than the first k value. The second low-k dielectric layer is overlying the first low-k dielectric layer. A dual damascene structure includes a via with a portion in the first low-k dielectric layer, and a metal line over and joined to the via. The metal line includes a portion in the second low-k dielectric layer.

公开(公告)号：US10707165B2

公开(公告)日：2020-07-07

申请号：US15492243

申请日：2017-04-20

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Po-Cheng Shih ,  Chia Cheng Chou ,  Li Chun Te

IPC: H01L23/532 ,  H01L21/02 ,  H01L21/768 ,  H01L23/522

Abstract: A method for manufacturing an extra low-k (ELK) inter-metal dielectric (IMD) layer includes forming a first IMD layer including a plurality of dielectric material layers over a substrate. An adhesion layer is formed over the first IMD layer. An ELK dielectric layer is formed over the adhesion layer. A protection layer is formed over the ELK dielectric layer. A hard mask is formed over the protection layer and is patterned to create a window. Layers underneath the window are removed to create an opening. The removed layers include the protection layer, the ELK dielectric layer, the adhesion layer, and the first IMD layer. A metal layer is formed in the opening.

公开(公告)号：US20200006059A1

公开(公告)日：2020-01-02

申请号：US16569791

申请日：2019-09-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia Cheng Chou ,  Po-Cheng Shih ,  Li Chun Te ,  Tien-I Bao

IPC: H01L21/02 ,  H01L21/311 ,  H01L21/768 ,  C23C16/30 ,  H01L23/532 ,  H01L23/535

Abstract: Embodiments described herein relate generally to methods for forming low-k dielectrics and the structures formed thereby. In some embodiments, a dielectric is formed over a semiconductor substrate. The dielectric has a k-value equal to or less than 3.9. Forming the dielectric includes using a plasma enhanced chemical vapor deposition (PECVD). The PECVD includes flowing a diethoxymethylsilane (mDEOS, C5H14O2Si) precursor gas, flowing an oxygen (O2) precursor gas; and flowing a carrier gas. A ratio of a flow rate of the mDEOS precursor gas to a flow rate of the carrier gas is less than or equal to 0.2.