公开(公告)号：US11488898B2

公开(公告)日：2022-11-01

申请号：US16942141

申请日：2020-07-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Po-Yao Lin ,  Shin-Puu Jeng

IPC: H01L23/48 ,  H01L23/498 ,  H01L23/00 ,  G06F30/3953 ,  G06F119/18

Abstract: A structure includes a first package component including a first conductive pad, and a second package component overlying the first package component. The second package component includes a surface dielectric layer, and a conductive bump protruding lower than the surface dielectric layer. The first conductive bump includes a first sidewall facing away from a center of the first package component, and a second sidewall facing toward the center. A solder bump joins the first conductive pad to the first conductive bump. The solder bump contacts the first sidewall. An underfill is between the first package component and the second package component, and the underfill contacts the second sidewall.

公开(公告)号：US11355474B2

公开(公告)日：2022-06-07

申请号：US16907180

申请日：2020-06-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Feng-Cheng Hsu ,  Shin-Puu Jeng

IPC: H01L25/065 ,  H01L23/31 ,  H01L25/00 ,  H01L21/56 ,  H01L23/48 ,  H01L21/683 ,  H01L25/10 ,  H01L23/29 ,  H01L21/768

Abstract: A semiconductor package including an insulating encapsulation, an integrated circuit component, and conductive elements is provided. The integrated circuit component is encapsulated in the insulating encapsulation, wherein the integrated circuit component has at least one through silicon via protruding from the integrated circuit component. The conductive elements are located on the insulating encapsulation, wherein one of the conductive elements is connected to the at least one through silicon via, and the integrated circuit component is electrically connected to the one of the conductive elements through the at least one through silicon via.

公开(公告)号：US20220165587A1

公开(公告)日：2022-05-26

申请号：US17669184

申请日：2022-02-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Feng-Cheng Hsu ,  Shuo-Mao Chen ,  Jui-Pin Hung ,  Shin-Puu Jeng

IPC: H01L21/56 ,  H01L21/78 ,  H01L23/00 ,  H01L23/31 ,  H01L23/538 ,  H01L21/683 ,  H01L25/00

Abstract: An embodiment device package includes a first die, a second die, and a molding compound extending along sidewalls of the first die and the second die. The package further includes redistribution layers (RDLs) extending laterally past edges of the first die and the second die. The RDLs include an input/output (I/O) contact electrically connected to the first die and the second die, and the I/O contact is exposed at a sidewall of the device package substantially perpendicular to a surface of the molding compound opposite the RDLs.

公开(公告)号：US11322449B2

公开(公告)日：2022-05-03

申请号：US15874374

申请日：2018-01-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shin-Puu Jeng ,  Po-Hao Tsai ,  Po-Yao Chuang ,  Techi Wong

IPC: H01L23/538 ,  H01L23/31 ,  H01L25/10 ,  H01L23/00 ,  H01L21/48 ,  H01L21/56 ,  H01L25/00 ,  H01L23/16 ,  H01L21/683

Abstract: Structures and formation methods of chip packages are provided. The method includes disposing a semiconductor die over a carrier substrate. The method also includes disposing an interposer substrate over the carrier substrate. The interposer substrate has a recess that penetrates through opposite surfaces of the interposer substrate. The interposer substrate has interior sidewalls surrounding the semiconductor die, and the semiconductor die is as high as or higher than the interposer substrate. The method further includes forming a protective layer in the recess of the interposer substrate to surround the semiconductor die. In addition, the method includes removing the carrier substrate and stacking a package structure over the interposer substrate.

公开(公告)号：US20220020693A1

公开(公告)日：2022-01-20

申请号：US17126881

申请日：2020-12-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shu-Shen Yeh ,  Che-Chia Yang ,  Chia-Kuei Hsu ,  Po-Yao Lin ,  Shin-Puu Jeng ,  Chia-Hsiang Lin

IPC: H01L23/538 ,  H01L23/00 ,  H01L21/768 ,  H01L21/48

Abstract: A method includes forming a first dielectric layer, forming a first redistribution line including a first via extending into the first dielectric layer, and a first trace over the first dielectric layer, forming a second dielectric layer covering the first redistribution line, and patterning the second dielectric layer to form a via opening. The first redistribution line is revealed through the via opening. The method further includes depositing a conductive material into the via opening to form a second via in the second dielectric layer, and a conductive pad over and contacting the second via, and forming a conductive bump over the conductive pad. The conductive pad is larger than the conductive bump, and the second via is offset from a center line of the conductive bump.

公开(公告)号：US20210327854A1

公开(公告)日：2021-10-21

申请号：US17361791

申请日：2021-06-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  Shin-Puu Jeng ,  Der-Chyang Yeh ,  Hsien-Wei Chen ,  Jie Chen

IPC: H01L25/065 ,  H01L23/538 ,  H01L23/00 ,  H01L25/10 ,  H01L23/50 ,  H01L23/48

Abstract: A package includes a corner, a device die, a plurality of redistribution lines underlying the device die, and a plurality of metal pads electrically coupled to the plurality of redistribution lines. The plurality of metal pads includes a corner metal pad closest to the corner, wherein the corner metal pad is a center-facing pad having a bird-beak direction substantially pointing to a center of the package. The plurality of metal pads further includes a metal pad farther away from the corner than the corner metal pad, wherein the metal pad is a non-center-facing pad having a bird-beak direction pointing away from the center of the package.

公开(公告)号：US11075132B2

公开(公告)日：2021-07-27

申请号：US15939314

申请日：2018-03-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shin-Puu Jeng ,  Hsien-Wen Liu ,  Shih-Ting Hung ,  Yi-Jou Lin ,  Tzu-Jui Fang ,  Po-Yao Chuang

IPC: H01L23/31 ,  H01L21/56 ,  H01L21/48 ,  H01L23/528 ,  H01L25/00 ,  H01L23/538 ,  H01L23/00 ,  H01L25/065 ,  H01L25/10

Abstract: An integrated fan-out package includes a first redistribution structure, a die, an encapsulant, a plurality of conductive structures, and a second redistribution structure. The first redistribution structure has a first surface and a second surface opposite to the first surface. The die is disposed over the first surface of the first redistribution structure and is electrically connected to the first redistribution structure. The encapsulant encapsulates the die. The conductive structures are disposed on the first surface of the first redistribution structure and penetrates the encapsulant. The conductive structures surround the die. The second redistribution structure is disposed on the encapsulant and is electrically connected to the first redistribution structure through the conductive structures. The second redistribution structure includes at least one conductive pattern layer that is in physical contact with the encapsulant.

公开(公告)号：US20210225776A1

公开(公告)日：2021-07-22

申请号：US16921907

申请日：2020-07-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Wen Wu ,  Shin-Puu Jeng ,  Shih-Ting Hung ,  Po-Yao Chuang

IPC: H01L23/552 ,  H01L23/538 ,  H01L25/16 ,  H01L23/31 ,  H01L25/00 ,  H01L21/48 ,  H01L21/56

Abstract: A package structure includes a redistribution structure, a first semiconductor die, a first passive component, a second semiconductor die, a first insulating encapsulant, a second insulating encapsulant, a second passive component and a global shielding structure. The redistribution structure includes dielectric layers and conductive layers alternately stacked. The first semiconductor die, the first passive component and the second semiconductor die are disposed on a first surface of the redistribution structure. The first insulating encapsulant is encapsulating the first semiconductor die and the first passive component. The second insulating encapsulant is encapsulating the second semiconductor die, wherein the second insulating encapsulant is separated from the first insulating encapsulant. The second passive component is disposed on a second surface of the redistribution structure. The global shielding structure is surrounding the first insulating encapsulant, the second insulating encapsulant, and covering sidewalls of the redistribution structure.

公开(公告)号：US11062997B2

公开(公告)日：2021-07-13

申请号：US16180511

申请日：2018-11-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shin-Puu Jeng ,  Techi Wong ,  Po-Yao Lin ,  Ming-Chih Yew ,  Po-Hao Tsai ,  Po-Yao Chuang

IPC: H01L23/538 ,  H01L23/00 ,  H01L21/48 ,  H01L25/00 ,  H01L21/683 ,  H01L25/10 ,  H01L23/31 ,  H01L21/768

Abstract: A method for forming a chip package structure is provided. The method includes forming a conductive pillar over a redistribution structure. The method includes bonding a chip to the redistribution structure. The method includes forming a molding layer over the redistribution structure. The molding layer surrounds the conductive pillar and the chip, and the conductive pillar passes through the molding layer. The method includes forming a cap layer over the molding layer and the conductive pillar. The cap layer has a through hole exposing the conductive pillar, and the cap layer includes fibers. The method includes forming a conductive via structure in the through hole. The conductive via structure is connected to the conductive pillar.

公开(公告)号：US11011447B2

公开(公告)日：2021-05-18

申请号：US16275518

申请日：2019-02-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chin-Hua Wang ,  Po-Yao Lin ,  Feng-Cheng Hsu ,  Shin-Puu Jeng ,  Wen-Yi Lin ,  Shu-Shen Yeh

IPC: H01L23/34 ,  H01L23/367 ,  H01L25/065 ,  H01L23/373 ,  H01L23/31 ,  H01L25/10 ,  H01L21/48 ,  H01L21/56 ,  H01L23/433

Abstract: A semiconductor package is provided. The semiconductor package includes a package substrate. The semiconductor package further includes a first chip and a second chip mounted on the package substrate. The thickness of the first chip is different from that of the second chip. In addition, the semiconductor package includes a heat spreader attached on top of the first chip and top of the second chip. A first portion of the heat spreader over the first chip and a second portion of the heat spreader over the second chip have the same thickness.