公开(公告)号：US12148684B2

公开(公告)日：2024-11-19

申请号：US17126598

申请日：2020-12-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shu-Shen Yeh ,  Che-Chia Yang ,  Chin-Hua Wang ,  Chia-Kuei Hsu ,  Po-Yao Lin ,  Shin-Puu Jeng

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/00

Abstract: A package structure and a method of forming the same are provided. The package structure includes an integrated circuit die and a redistribution structure bonded to the integrated circuit die. The redistribution structure includes a first insulating layer, a second insulating layer interposed between the first insulating layer and the integrated circuit die, and a first metallization pattern in the first insulating layer and the second insulating layer. The first metallization pattern includes a first conductive line and a first conductive via coupled to the first conductive line. The first conductive line is in the second insulating layer. The first conductive via is in the first insulating layer. The first conductive line includes a first conductive pad coupled to the first conductive via, a second conductive pad, and a curved portion connecting the first conductive pad to the second conductive pad.

公开(公告)号：US11855008B2

公开(公告)日：2023-12-26

申请号：US17818729

申请日：2022-08-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shu-Shen Yeh ,  Che-Chia Yang ,  Chin-Hua Wang ,  Po-Yao Lin ,  Shin-Puu Jeng ,  Chia-Hsiang Lin

IPC: H01L23/00 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31 ,  H01L23/538 ,  H01L23/48 ,  H01L25/065

CPC classification number: H01L23/562 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/563 ,  H01L23/3107 ,  H01L23/3185 ,  H01L23/481 ,  H01L23/5383 ,  H01L23/5386 ,  H01L23/5389 ,  H01L24/13 ,  H01L24/16 ,  H01L25/0657 ,  H01L2224/12105 ,  H01L2224/16227 ,  H01L2924/18161 ,  H01L2924/351 ,  H01L2924/35121

Abstract: A method includes forming a first dielectric layer, forming a first redistribution line comprising a first via extending into the first dielectric layer, and a first trace over the first dielectric layer, forming a second dielectric layer covering the first redistribution line, and patterning the second dielectric layer to form a via opening. The first redistribution line is revealed through the via opening. The method further includes forming a second via in the second dielectric layer, and a conductive pad over and contacting the second via, and forming a conductive bump over the conductive pad. The conductive pad is larger than the conductive bump, with a first center of conductive pad being offsetting from a second center of the conductive bump. The second via is further offset from the second center of the conductive bump.

公开(公告)号：US20230387063A1

公开(公告)日：2023-11-30

申请号：US17664689

申请日：2022-05-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Sheng Lin ,  Shu-Shen Yeh ,  Ming-Chih Yew ,  Chin-Hua Wang ,  Shin-Puu Jeng

IPC: H01L23/00 ,  H01L25/065 ,  H01L23/498

CPC classification number: H01L24/32 ,  H01L24/27 ,  H01L25/0655 ,  H01L23/49833 ,  H01L2924/3511 ,  H01L2924/35121 ,  H01L2924/37001 ,  H01L24/16 ,  H01L24/73 ,  H01L2224/73204 ,  H01L2224/16227 ,  H01L2224/16237 ,  H01L2224/32225 ,  H01L2224/26155 ,  H01L2224/3201 ,  H01L2224/27013 ,  H01L2924/1436 ,  H01L2924/1431 ,  H01L23/49838 ,  H01L23/49822 ,  H01L23/49816

Abstract: A package includes a package substrate, the package substrate having a first side and a second side opposite to the first side, a package component bonded to the first side of the package substrate, a front-side warpage control structure attached to the first side of the package substrate, and a backside warpage control structure embedded in the package substrate from the second side of the package substrate. The front-side warpage control structure includes a first disconnected structure and a second disconnected structure laterally separated from each other by a gap. The backside warpage control structure includes a third disconnected structure and a fourth disconnected structure laterally separated from each other.

公开(公告)号：US20220246490A1

公开(公告)日：2022-08-04

申请号：US17246035

申请日：2021-04-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shu-Shen Yeh ,  Chin-Hua Wang ,  Chia-Kuei Hsu ,  Po-Yao Lin ,  Shin-Puu Jeng

IPC: H01L23/367 ,  H01L25/065 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L21/48 ,  H01L21/56 ,  H01L25/00

Abstract: Semiconductor devices and methods of manufacture which utilize lids in order to constrain thermal expansion during annealing are presented. In some embodiments lids are placed and attached on encapsulant and, in some embodiments, over first semiconductor dies. As such, when heat is applied, and the encapsulant attempts to expand, the lid will work to constrain the expansion, reducing the amount of stress that would otherwise accumulate within the encapsulant.

公开(公告)号：US10797006B2

公开(公告)日：2020-10-06

申请号：US16200838

申请日：2018-11-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shu-Shen Yeh ,  Chin-Hua Wang ,  Kuang-Chun Lee ,  Po-Yao Lin ,  Shyue-Ter Leu ,  Shin-Puu Jeng

IPC: H01L23/00 ,  H01L23/367 ,  H01L23/04 ,  H01L23/10 ,  H01L23/498

Abstract: Structures and formation methods of a chip package are provided. The chip package includes a substrate and a semiconductor die over the substrate. The chip package also includes a lid covering a top surface of the semiconductor die. The lid has multiple support structures, and the support structures are positioned at respective corner portions of the substrate. Multiple openings penetrate through the lid to expose a space containing the semiconductor die.

公开(公告)号：US09870975B1

公开(公告)日：2018-01-16

申请号：US15210343

申请日：2016-07-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chin-Hua Wang ,  Po-Yao Lin ,  Shu-Shen Yeh ,  Kuang-Chun Lee ,  Shin-Puu Jeng ,  Shyue-Ter Leu ,  Cheng-Lin Huang ,  Hsiu-Mei Yu

IPC: H01L23/34 ,  H01L23/373 ,  H01L25/065 ,  H01L23/31 ,  H01L23/00

CPC classification number: H01L23/3736 ,  H01L23/3107 ,  H01L23/3157 ,  H01L24/17 ,  H01L24/48 ,  H01L24/49 ,  H01L25/0657 ,  H01L2224/48221 ,  H01L2224/4909 ,  H01L2225/06541

Abstract: Structures and formation methods of a chip package are provided. The chip package includes a first package structure including a first semiconductor die that has a first side and a second side opposite thereto. The chip package also includes a package layer partially or completely encapsulating the first semiconductor die, and a conductive feature in the package layer. The chip package further includes a first heat-spreading layer over the first side of the first semiconductor die and a first cap layer on the first heat-spreading layer.

公开(公告)号：US20240088061A1

公开(公告)日：2024-03-14

申请号：US18517489

申请日：2023-11-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shu-Shen Yeh ,  Che-Chia Yang ,  Chin-Hua Wang ,  Po-Yao Lin ,  Shin-Puu Jeng ,  Chia-Hsiang Lin

IPC: H01L23/00 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31 ,  H01L23/48 ,  H01L23/538 ,  H01L25/065

CPC classification number: H01L23/562 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/563 ,  H01L23/3107 ,  H01L23/3185 ,  H01L23/481 ,  H01L23/5383 ,  H01L23/5386 ,  H01L23/5389 ,  H01L24/13 ,  H01L24/16 ,  H01L25/0657 ,  H01L2224/12105 ,  H01L2224/16227 ,  H01L2924/18161 ,  H01L2924/351 ,  H01L2924/35121

Abstract: A method includes forming a first dielectric layer, forming a first redistribution line comprising a first via extending into the first dielectric layer, and a first trace over the first dielectric layer, forming a second dielectric layer covering the first redistribution line, and patterning the second dielectric layer to form a via opening. The first redistribution line is revealed through the via opening. The method further includes forming a second via in the second dielectric layer, and a conductive pad over and contacting the second via, and forming a conductive bump over the conductive pad. The conductive pad is larger than the conductive bump, with a first center of conductive pad being offsetting from a second center of the conductive bump. The second via is further offset from the second center of the conductive bump.

公开(公告)号：US20230402339A1

公开(公告)日：2023-12-14

申请号：US17840362

申请日：2022-06-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shu-Shen Yeh ,  Chin-Hua Wang ,  Chipta Priya Laksana ,  Po-Yao Lin ,  Shin-Puu Jeng

IPC: H01L23/31 ,  H01L23/538 ,  H01L23/16 ,  H01L23/00 ,  H01L21/48 ,  H01L21/56

CPC classification number: H01L23/3128 ,  H01L23/3135 ,  H01L23/5383 ,  H01L23/16 ,  H01L23/562 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/563 ,  H01L21/565

Abstract: In an embodiment, a method of forming a semiconductor device includes: attaching an integrated circuit die to an interposer; forming an encapsulant over the interposer and around the integrated circuit die, a top surface of the encapsulant and a top surface of the integrated circuit die being level; forming recesses in the encapsulant; and bonding the interposer to a package substrate, wherein after bonding the interposer to the package substrate, each of the recesses being along an outer edge of the encapsulant.

公开(公告)号：US11011447B2

公开(公告)日：2021-05-18

申请号：US16275518

申请日：2019-02-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chin-Hua Wang ,  Po-Yao Lin ,  Feng-Cheng Hsu ,  Shin-Puu Jeng ,  Wen-Yi Lin ,  Shu-Shen Yeh

IPC: H01L23/34 ,  H01L23/367 ,  H01L25/065 ,  H01L23/373 ,  H01L23/31 ,  H01L25/10 ,  H01L21/48 ,  H01L21/56 ,  H01L23/433

Abstract: A semiconductor package is provided. The semiconductor package includes a package substrate. The semiconductor package further includes a first chip and a second chip mounted on the package substrate. The thickness of the first chip is different from that of the second chip. In addition, the semiconductor package includes a heat spreader attached on top of the first chip and top of the second chip. A first portion of the heat spreader over the first chip and a second portion of the heat spreader over the second chip have the same thickness.

公开(公告)号：US20240387339A1

公开(公告)日：2024-11-21

申请号：US18787212

申请日：2024-07-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shu-Shen Yeh ,  Che-Chia Yang ,  Chin-Hua Wang ,  Chia-Kuei Hsu ,  Po-Yao Lin ,  Shin-Puu Jeng

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/00

Abstract: A package structure and a method of forming the same are provided. The package structure includes an integrated circuit die and a redistribution structure bonded to the integrated circuit die. The redistribution structure includes a first insulating layer, a second insulating layer interposed between the first insulating layer and the integrated circuit die, and a first metallization pattern in the first insulating layer and the second insulating layer. The first metallization pattern includes a first conductive line and a first conductive via coupled to the first conductive line. The first conductive line is in the second insulating layer. The first conductive via is in the first insulating layer. The first conductive line includes a first conductive pad coupled to the first conductive via, a second conductive pad, and a curved portion connecting the first conductive pad to the second conductive pad.