公开(公告)号：US20230268224A1

公开(公告)日：2023-08-24

申请号：US18309131

申请日：2023-04-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-Jen Lo ,  Po-Cheng Shih ,  Syun-Ming Jang ,  Tze-Liang Lee

IPC: H01L21/768 ,  H01L21/027 ,  G03F7/20 ,  G03F7/038 ,  G03F7/039

CPC classification number: H01L21/76823 ,  H01L21/76802 ,  H01L21/0274 ,  G03F7/2022 ,  G03F7/038 ,  G03F7/039 ,  G03F7/2004 ,  H01L21/76877

Abstract: A representative method includes forming a photo-sensitive material over a substrate, and forming a cap layer over the photo-sensitive material, and patterning the cap layer. Using the patterned cap layer, a first portion of the photo-sensitive material is selectively exposed to a pre-selected light wavelength to change at least one material property of the first portion of the photo-sensitive material, while preventing a second portion of the photo-sensitive material from being exposed to the pre-selected light wavelength. One, but not both of the following steps is then conducted: removing the first portion of the photo-sensitive material and forming in its place a conductive element at least partially surrounded by the second portion of the photo-sensitive material, or removing the second portion of the photo-sensitive material and forming from the first portion of the photo-sensitive material a conductive element electrically connecting two or more portions of a circuit.

公开(公告)号：US10854729B2

公开(公告)日：2020-12-01

申请号：US16578360

申请日：2019-09-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tsan-Chun Wang ,  Ziwei Fang ,  Chii-Horng Li ,  Tze-Liang Lee ,  Chao-Cheng Chen ,  Syun-Ming Jang

IPC: H01L29/66 ,  H01L29/10 ,  H01L29/165 ,  H01L21/8238 ,  H01L21/306 ,  H01L21/3065 ,  H01L21/265

Abstract: The present disclosure relates to a method of forming a transistor device. In this method, first and second well regions are formed within a semiconductor substrate. The first and second well regions have first and second etch rates, respectively, which are different from one another. Dopants are selectively implanted into the first well region to alter the first etch rate to make the first etch rate substantially equal to the second etch rate. The first, selectively implanted well region and the second well region are etched to form channel recesses having equal recess depths. An epitaxial growth process is performed to form one or more epitaxial layers within the channel recesses.

公开(公告)号：US10692814B2

公开(公告)日：2020-06-23

申请号：US15401470

申请日：2017-01-09

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Wen-Jiun Liu ,  Chen-Yuan Kao ,  Hung-Wen Su ,  Ming-Hsing Tsai ,  Syun-Ming Jang

IPC: H01L23/532 ,  H01L21/768 ,  H01L21/288 ,  H01L23/528 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/3213 ,  H01L23/522

Abstract: A semiconductor structure with an improved metal structure is described. The semiconductor structure can include a substrate having an upper surface, an interconnect layer over the upper surface, and an additional structure deposited over the interconnect layer. The interconnect layer can include a patterned seed layer over the substrate, at least two metal lines over the seed layer, and a dielectric material between adjacent metal lines. A barrier layer can be deposited over the at least two metal lines. Methods of making the semiconductor structures are also described.

公开(公告)号：US10262944B2

公开(公告)日：2019-04-16

申请号：US15370016

申请日：2016-12-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Chieh Lin ,  Hung-Wen Su ,  Ming-Hsing Tsai ,  Syun-Ming Jang

IPC: H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L29/51 ,  H01L21/768

Abstract: An interconnect layer is disposed over a substrate. The interconnect layer includes a plurality of dielectric segments interleaved with a plurality of metal components. A plurality of vias is disposed below, and electrically coupled to, a first group of the metal components. A plurality of dielectric components is disposed underneath a second group of the metal components. The dielectric components interleave with the vias. A conductive liner is disposed below a bottom surface and on sidewalk of the vias. A dielectric barrier layer is disposed below a bottom surface and on sidewalls of the dielectric segments. The dielectric barrier layer and the dielectric segments have different material compositions.

公开(公告)号：US09281196B2

公开(公告)日：2016-03-08

申请号：US14175194

申请日：2014-02-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tsan-Chun Wang ,  Ziwei Fang ,  Chii-Horng Li ,  Tze-Liang Lee ,  Chao-Cheng Chen ,  Syun-Ming Jang

IPC: H01L29/78 ,  H01L21/265 ,  H01L29/66 ,  H01L29/10 ,  H01L29/165 ,  H01L21/8238 ,  H01L21/306 ,  H01L21/3065

CPC classification number: H01L29/66537 ,  H01L21/26513 ,  H01L21/30608 ,  H01L21/3065 ,  H01L21/823807 ,  H01L21/823878 ,  H01L21/823892 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/66651

Abstract: The present disclosure relates to a method of forming a transistor device. In this method, first and second well regions are formed within a semiconductor substrate. The first and second well regions have first and second etch rates, respectively, which are different from one another. Dopants are selectively implanted into the first well region to alter the first etch rate to make the first etch rate substantially equal to the second etch rate. The first, selectively implanted well region and the second well region are etched to form channel recesses having equal recess depths. An epitaxial growth process is performed to form one or more epitaxial layers within the channel recesses.

Abstract translation: 本公开涉及一种形成晶体管器件的方法。 在该方法中，第一和第二阱区形成在半导体衬底内。 第一和第二阱区域分别具有彼此不同的第一和第二蚀刻速率。 将掺杂剂选择性地注入第一阱区以改变第一蚀刻速率以使第一蚀刻速率基本上等于第二蚀刻速率。 蚀刻第一选择性注入的阱区和第二阱区以形成具有相等凹槽深度的沟槽。 进行外延生长工艺以在通道凹槽内形成一个或多个外延层。

公开(公告)号：US20150187927A1

公开(公告)日：2015-07-02

申请号：US14175194

申请日：2014-02-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tsan-Chun Wang ,  Ziwei Fang ,  Chii-Horng Li ,  Tze-Liang Lee ,  Chao-Cheng Chen ,  Syun-Ming Jang

IPC: H01L29/78 ,  H01L21/265

CPC classification number: H01L29/66537 ,  H01L21/26513 ,  H01L21/30608 ,  H01L21/3065 ,  H01L21/823807 ,  H01L21/823878 ,  H01L21/823892 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/66651

Abstract: The present disclosure relates to a method of forming a transistor device. In this method, first and second well regions are formed within a semiconductor substrate. The first and second well regions have first and second etch rates, respectively, which are different from one another. Dopants are selectively implanted into the first well region to alter the first etch rate to make the first etch rate substantially equal to the second etch rate. The first, selectively implanted well region and the second well region are etched to form channel recesses having equal recess depths. An epitaxial growth process is performed to form one or more epitaxial layers within the channel recesses.

Abstract translation: 本公开涉及一种形成晶体管器件的方法。 在该方法中，第一和第二阱区形成在半导体衬底内。 第一和第二阱区域分别具有彼此不同的第一和第二蚀刻速率。 将掺杂剂选择性地注入第一阱区以改变第一蚀刻速率以使第一蚀刻速率基本上等于第二蚀刻速率。 蚀刻第一选择性注入的阱区和第二阱区以形成具有相等凹槽深度的沟槽。 进行外延生长工艺以在通道凹槽内形成一个或多个外延层。