公开(公告)号：US20210217868A1

公开(公告)日：2021-07-15

申请号：US17218307

申请日：2021-03-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Meng-Han Lin ,  Te-Hsin Chiu ,  Wei Cheng Wu

IPC: H01L29/423 ,  H01L29/10 ,  H01L29/78 ,  H01L29/08 ,  H01L29/66 ,  H01L21/762 ,  H01L29/06 ,  H01L21/28

Abstract: The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes an isolation structure arranged within a substrate. The isolation structure has one or more surfaces defining one or more trenches that are recessed below an uppermost surface of the isolation structure and that are disposed along opposing sides of an active region of the substrate. A conductive gate is arranged over the substrate between a source region and a drain region. The conductive gate extends into the one or more trenches disposed along opposing sides of the active region of the substrate. The conductive gate has an upper surface that continuously extends past opposing sides of the one or more trenches.

公开(公告)号：US11063044B2

公开(公告)日：2021-07-13

申请号：US16906031

申请日：2020-06-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Meng-Han Lin ,  Te-Hsin Chiu ,  Wei Cheng Wu

IPC: H01L21/00 ,  H01L27/092 ,  H01L29/49 ,  H01L29/423 ,  H01L29/78 ,  H01L21/8238 ,  H01L29/66 ,  H01L21/28 ,  H01L21/762 ,  H01L29/40 ,  H01L29/51

Abstract: The present disclosure relates to a method of forming an integrated chip. The method includes forming an isolation structure within a substrate. The isolation structure surrounds a device region of the substrate. A sacrificial gate material is formed over the isolation structure and the device region of the substrate. A part of the sacrificial gate material is removed and a second metal is deposited where the part of the sacrificial gate material was removed. A remainder of the sacrificial gate material is subsequently removed and a first metal is deposited where the remainder of the sacrificial gate material was removed. The first metal is different than the second metal.

公开(公告)号：US10998315B2

公开(公告)日：2021-05-04

申请号：US16887138

申请日：2020-05-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Meng-Han Lin ,  Te-Hsin Chiu ,  Wei Cheng Wu

IPC: H01L29/00 ,  H01L27/092 ,  H01L29/49 ,  H01L29/423 ,  H01L29/78 ,  H01L21/8238 ,  H01L29/66 ,  H01L21/28 ,  H01L21/762 ,  H01L29/40 ,  H01L29/51

Abstract: The present disclosure relates to an integrated chip. The integrated chip includes a source region and a drain region disposed within an upper surface of a substrate. One or more dielectric materials are disposed within a trench within the substrate. The trench surrounds the source region and the drain region. A gate structure is disposed over the substrate between the source region and the drain region. The gate structure includes a first gate metal having a first sidewall and a second gate metal having a first outer sidewall that contacts the first sidewall directly over the upper surface of the substrate.

公开(公告)号：US10957704B2

公开(公告)日：2021-03-23

申请号：US16734691

申请日：2020-01-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Harry-Hak-Lay Chuang ,  Wei Cheng Wu ,  Ya-Chen Kao ,  Yi Hsien Lu

IPC: H01L29/792 ,  H01L27/11573 ,  H01L29/66 ,  H01L29/423 ,  H01L29/51 ,  H01L21/8234 ,  H01L27/092 ,  H01L27/088

Abstract: The present disclosure relates to a structure and method for embedding a non-volatile memory (NVM) in a HKMG (high-κ metal gate) integrated circuit which includes a high-voltage (HV) HKMG transistor. NVM devices (e.g., flash memory) are operated at high voltages for its read and write operations and hence a HV device is necessary for integrated circuits involving non-volatile embedded memory and HKMG logic circuits. Forming a HV HKMG circuit along with the HKMG periphery circuit reduces the need for additional boundaries between the HV transistor and rest of the periphery circuit. This method further helps reduce divot issue and reduce cell size.

公开(公告)号：US20210083042A1

公开(公告)日：2021-03-18

申请号：US17106409

申请日：2020-11-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Meng-Han Lin ,  Te-Hsin Chiu ,  Wei Cheng Wu ,  Te-An Chen

IPC: H01L49/02 ,  H01L21/8234 ,  H01L27/06 ,  H01L27/08

Abstract: A semiconductor device and a manufacturing method thereof are provided. The semiconductor device has a substrate having an isolation structure therein and a capacitor structure located on an upper top surface of the isolation structure. The capacitor structure comprises a first semiconductor structure and a second semiconductor structure respectively disposed on the upper surface of the isolation structure and separated by an insulator pattern.

公开(公告)号：US20200251566A1

公开(公告)日：2020-08-06

申请号：US16580296

申请日：2019-09-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei Cheng Wu ,  Alexander Kalnitsky ,  Shih-Hao Lo ,  Hung-Pin Ko

IPC: H01L29/423 ,  H01L29/66

Abstract: Various embodiments of the present disclosure are directed towards a semiconductor device including a gate structure. The semiconductor device further includes a pair of spacer segments on a semiconductor substrate. A high-κ gate dielectric structure overlies the semiconductor substrate. The high-κ gate dielectric structure is laterally between and borders the spacer segments. The gate structure overlies the high-k gate dielectric structure and has a top surface about even with a top surface of the spacer segments. The gate structure includes a metal structure and a gate body layer. The gate body layer has a top surface that is vertically offset from a top surface of the metal structure and further has a lower portion cupped by the metal structure.

公开(公告)号：US10516026B2

公开(公告)日：2019-12-24

申请号：US16166603

申请日：2018-10-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chang-Ming Wu ,  Wei Cheng Wu ,  Shih-Chang Liu ,  Harry-Hak-Lay Chuang ,  Chia-Shiung Tsai

IPC: H01L29/423 ,  H01L27/11521 ,  H01L27/1157 ,  H01L27/11524 ,  H01L27/11568 ,  H01L29/66 ,  H01L21/28 ,  H01L29/792 ,  H01L29/51

Abstract: The present disclosure, in some embodiments, relates to a method of forming a memory cell. The method may be performed by forming a select gate on a side of a sacrificial spacer that is disposed over an upper surface of a substrate. The select gate has a non-planar top surface. An inter-gate dielectric layer is formed on the select gate and a memory gate is formed on the inter-gate dielectric layer. The inter-gate dielectric layer extends under the memory gate and defines a recess between sidewalls of the memory gate and select gate. The recess is filled with a first dielectric material.

公开(公告)号：US10515977B2

公开(公告)日：2019-12-24

申请号：US16033357

申请日：2018-07-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei Cheng Wu ,  Chien-Hung Chang

IPC: H01L27/11575 ,  H01L29/06

Abstract: In some embodiments, the present disclosure relates to an integrated chip. The integrated chip includes a logic region having a plurality of transistor devices disposed within a substrate, an embedded memory region having a plurality of memory devices disposed within the substrate, and a boundary region separating the logic region from the embedded memory region. The boundary region includes a first isolation structure having a first upper surface and a second upper surface below the first upper surface. The first and second upper surfaces are coupled by an interior sidewall overlying the first isolation structure. The boundary region further includes a memory wall arranged on the second upper surface and surrounding the embedded memory region, and a logic wall arranged on the first upper surface and surrounding the memory wall. The logic wall has an upper surface that is above the plurality of memory devices and the memory wall.

公开(公告)号：US10325919B1

公开(公告)日：2019-06-18

申请号：US16015480

申请日：2018-06-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Li-Feng Teng ,  Wei Cheng Wu

IPC: H01L27/115 ,  H01L27/11546 ,  H01L27/11529 ,  H01L27/11524

Abstract: Various embodiments of the present application are directed to a method for forming an integrated circuit (IC), and the associated integrated circuit. In some embodiments, a stack of gate dielectric precursor layers is formed on a plurality of logic sub-region and is then selectively removed from at least two logic sub-regions. Then, a gate dielectric precursor layer is formed, and a plasma treatment process and an annealing process are subsequently performed. The gate dielectric precursor layer is then selectively removed from a low-voltage logic sub-region, but not a high-voltage logic sub-region. By removing the stack of gate dielectric precursor layers from the low-voltage logic sub-region prior to performing the plasma treatment process and the annealing process, less gate dielectric precursor material is treated, annealed, and removed from the low-voltage logic sub-region. Thus, the resulting residues are reduced, and the defects introduced by the residues are also reduced or eliminated.

公开(公告)号：US20190148375A1

公开(公告)日：2019-05-16

申请号：US15989648

申请日：2018-05-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Meng-Han Lin ,  Te-Hsin Chiu ,  Wei Cheng Wu

IPC: H01L27/092 ,  H01L29/49 ,  H01L29/423 ,  H01L29/78 ,  H01L29/40 ,  H01L29/66 ,  H01L21/28 ,  H01L21/762 ,  H01L21/8238

Abstract: In some embodiments, the present disclosure, relates to an integrated chip. The integrated chip has an isolation structure arranged within a substrate. The isolation structure has interior surfaces defining one or more divots recessed below an uppermost surface of the isolation structure and sidewalls defining an opening exposing the substrate. A source region is disposed within the opening. A drain region is also disposed within the opening and is separated from the source region by a channel region along a first direction. A gate structure extends over the channel region. The gate structure includes a first gate electrode region having a first composition of one or more materials and a second gate electrode region disposed over the one or more divots and having a second composition of one or more materials different than the first composition of one or more materials.