公开(公告)号：US11264204B2

公开(公告)日：2022-03-01

申请号：US17080391

申请日：2020-10-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Hsiung Lin ,  Cheng-En Lee ,  Chia-Lin Ou ,  Hsuan-Pang Liu ,  Yao-Jen Yeh

IPC: H01J37/317 ,  H01J37/08 ,  H01J37/30

Abstract: The present disclosure relates to a method includes generating ions with an ion source of an ion implantation apparatus based on an ion implantation recipe. The method includes accelerating the generated ions based on an ion energy setting in the ion implantation recipe and determining an energy spectrum of the accelerated ions. The method also includes analyzing a relationship between the determined energy spectrum and the ion energy setting. The method further includes adjusting at least one parameter of a final energy magnet (FEM) of the ion implantation apparatus based on the analyzed relationship.

公开(公告)号：US20210242212A1

公开(公告)日：2021-08-05

申请号：US17234256

申请日：2021-04-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Pochun Wang ,  Ting-Wei Chiang ,  Chih-Ming Lai ,  Hui-Zhong Zhuang ,  Jung-Chan Yang ,  Ru-Gun Liu ,  Shih-Ming Chang ,  Ya-Chi Chou ,  Yi-Hsiung Lin ,  Yu-Xuan Huang ,  Guo-Huei Wu ,  Yu-Jung Chang

IPC: H01L27/108 ,  H01L29/78 ,  H01L21/8238 ,  H01L27/092 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L27/02

Abstract: An integrated circuit includes a semiconductor substrate, an isolation region extending into, and overlying a bulk portion of, the semiconductor substrate, a buried conductive track comprising a portion in the isolation region, and a transistor having a source/drain region and a gate electrode. The source/drain region or the gate electrode is connected to the buried conductive track.

公开(公告)号：US10727113B2

公开(公告)日：2020-07-28

申请号：US16704195

申请日：2019-12-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ethan Hsiao ,  Chien Wen Lai ,  Chih-Ming Lai ,  Yi-Hsiung Lin ,  Cheng-Chi Chuang ,  Hsin-Ping Chen ,  Ru-Gun Liu

IPC: H01L21/768 ,  H01L21/33 ,  H01L21/027 ,  H01L21/033 ,  H01L21/311 ,  H01L21/8234 ,  H01L21/3105

Abstract: A method includes providing a substrate comprising a material layer and a hard mask layer; patterning the hard mask layer to form hard mask lines; forming a spacer layer over the substrate, including over the hard mask lines, resulting in trenches defined by the spacer layer, wherein the trenches track the hard mask lines; forming a antireflective layer over the spacer layer, including over the trenches; forming an L-shaped opening in the antireflective layer, thereby exposing at least two of the trenches; filling the L-shaped opening with a fill material; etching the spacer layer to expose the hard mask lines; removing the hard mask lines; after removing the hard mask lines, transferring a pattern of the spacer layer and the fill material onto the material layer, resulting in second trenches tracking the pattern; and filling the second trenches with a conductive material.

公开(公告)号：US20200006160A1

公开(公告)日：2020-01-02

申请号：US16393543

申请日：2019-04-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Hsiung Lin ,  Yi-Hsun Chiu ,  Shang-Wen Chang

IPC: H01L21/8238 ,  H01L27/092 ,  H01L21/768 ,  H01L29/08 ,  H01L29/66 ,  H01L29/78 ,  H01L21/762 ,  H01L23/522

Abstract: A method includes forming an interlayer dielectric (ILD) layer over a first epitaxial source/drain (S/D) feature and a second epitaxial S/D feature, where the first epitaxial S/D feature is disposed adjacent to the second epitaxial S/D feature, forming a dummy contact feature in the ILD layer over the first epitaxial S/D feature, removing a portion of the dummy contact feature and a portion of the ILD layer disposed above the second epitaxial S/D feature to form a first trench, removing a remaining portion of the dummy contact feature to form a second trench, and forming a metal S/D contact in the first and the second trenches.