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公开(公告)号：US12062408B2
公开(公告)日：2024-08-13
申请号：US18361542
申请日：2023-07-28
发明人： Meng-Sheng Chang , Chia-En Huang , Yi-Ching Liu , Yih Wang
IPC分类号： G11C5/06
CPC分类号： G11C5/063
摘要： Disclosed herein are related to a memory array including a set of memory cells and a set of switches to configure the set of memory cells. In one aspect, each switch is connected between a corresponding local line and a corresponding subset of memory cells. The local clines may be connected to a global line. Local lines may be metal rails, for example, local bit lines or local select lines. A global line may be a metal rail, for example, a global bit line or a global select line. A switch may be enabled or disabled to electrically couple a controller to a selected subset of memory cells through the global line. Accordingly, the set of memory cells can be configured through the global line rather than a number of metal rails to achieve area efficiency.
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公开(公告)号：US12002499B2
公开(公告)日：2024-06-04
申请号：US17868982
申请日：2022-07-20
发明人： Sheng-chen Wang , Meng-Han Lin , Chia-En Huang , Yi-Ching Liu
IPC分类号： G11C11/22 , H01L23/528 , H10B51/20 , H10B51/30
CPC分类号： G11C11/2259 , G11C11/223 , H01L23/528 , H10B51/20 , H10B51/30
摘要： Systems and methods disclosed herein are related to a memory system. In one aspect, the memory system includes a first set of memory cells including a first string of memory cells and a second string of memory cells; and a first switch including: a first electrode connected to first electrodes of the first string of memory cells and first electrodes of the second string of memory cells, and a second electrode connected to a first global bit line, wherein gate electrodes of the first string of memory cells are connected to a first word line and gate electrodes of the second string of memory cells are connected to a second word line.
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公开(公告)号：US20240090231A1
公开(公告)日：2024-03-14
申请号：US18516908
申请日：2023-11-21
发明人： Bo-Feng Young , Yi-Ching Liu , Sai-Hooi Yeong , Yih Wang , Yu-Ming Lin
IPC分类号： H10B51/40 , G11C11/22 , H01L23/522 , H10B43/30 , H10B43/40 , H10B43/50 , H10B51/20 , H10B51/30 , H10B51/50
CPC分类号： H10B51/40 , G11C11/2257 , H01L23/5226 , H10B43/30 , H10B43/40 , H10B43/50 , H10B51/20 , H10B51/30 , H10B51/50
摘要： An integrated circuit is provided. The integrated circuit includes a three-dimensional memory device, a first word line driving circuit and a second word line driving circuit. The three-dimensional memory device includes stacking structures separately extending along a column direction. Each stacking structure includes a stack of word lines. The stacking structures have first staircase structures at a first side and second staircase structures at a second side. The word lines extend to steps of the first and second staircase structures. The first and second word line driving circuits lie below the three-dimensional memory device, and extend along the first and second sides, respectively. Some of the word lines in each stacking structure are routed to the first word line driving circuit from a first staircase structure, and others of the word lines in each stacking structure are routed to the second word line driving circuit from a second staircase structure.
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公开(公告)号：US20240023338A1
公开(公告)日：2024-01-18
申请号：US18361270
申请日：2023-07-28
发明人： Peng-Chun Liou , Zhiqiang Wu , Ya-Yun Cheng , Yi-Ching Liu , Meng-Han Lin
摘要： A semiconductor device includes a first conductive structure extending along a vertical direction and a second conductive structure extending along the vertical direction. The second conductive structure is spaced apart from the first conductive structure along a first lateral direction. The semiconductor device includes third conductive structures each extending along the first lateral direction. The third conductive structures are disposed across the first and second conductive structures. The semiconductor device includes a first semiconductor channel extending along the vertical direction. The first semiconductor channel is disposed between the third conductive structures and the first conductive structure, and between the third conductive structures and the second conductive structure. The first and second conductive structures each have a first varying width along the first lateral direction, and the first semiconductor channel has a second varying width along a second lateral direction.
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公开(公告)号：US20240021220A1
公开(公告)日：2024-01-18
申请号：US18361542
申请日：2023-07-28
发明人： Meng-Sheng Chang , Chia-En Huang , Yi-Ching Liu , Yih Wang
IPC分类号： G11C5/06
CPC分类号： G11C5/063
摘要： Disclosed herein are related to a memory array including a set of memory cells and a set of switches to configure the set of memory cells. In one aspect, each switch is connected between a corresponding local line and a corresponding subset of memory cells. The local clines may be connected to a global line. Local lines may be metal rails, for example, local bit lines or local select lines. A global line may be a metal rail, for example, a global bit line or a global select line. A switch may be enabled or disabled to electrically couple a controller to a selected subset of memory cells through the global line. Accordingly, the set of memory cells can be configured through the global line rather than a number of metal rails to achieve area efficiency.
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公开(公告)号：US11854616B2
公开(公告)日：2023-12-26
申请号：US17460206
申请日：2021-08-28
发明人： Meng-Sheng Chang , Chia-En Huang , Yi-Ching Liu , Yih Wang
CPC分类号： G11C13/004 , G11C13/003 , G11C13/0026 , G11C13/0028
摘要： Disclosed herein are related to a memory array. In one aspect, the memory array includes a set of resistive storage circuits including a first subset of resistive storage circuits connected between a first local line and a second local line in parallel. The first local line and the second local line may extend along a first direction. In one aspect, for each resistive storage circuit of the first subset of resistive storage circuits, current injected at a first common entry point of the first local line exits through a first common exit point of the second local line, such that each resistive storage circuit of the first subset of resistive storage circuits may have same or substantial equal resistive loading.
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公开(公告)号：US20230386538A1
公开(公告)日：2023-11-30
申请号：US18446999
申请日：2023-08-09
发明人： Meng-Sheng Chang , Chia-En Huang , Yi-Ching Liu , Yih Wang
CPC分类号： G11C7/12 , G11C5/14 , H01L27/0688 , G11C5/025
摘要： Disclosed herein are related to a memory array. In one aspect, the memory array includes a first set of memory cells including a first subset of memory cells and a second subset of memory cells. In one aspect, the memory array includes a first switch including a first electrode connected to first electrodes of the first subset of memory cells, and a second electrode connected to a first global line. In one aspect, the memory array includes a second switch including a first electrode connected to first electrodes of the second subset of memory cells, and a second electrode connected to the first global line.
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公开(公告)号：US20230345732A1
公开(公告)日：2023-10-26
申请号：US18346278
申请日：2023-07-03
发明人： Meng-Han Lin , Han-Jong Chia , Yi-Ching Liu , Chia-En Huang , Sheng-Chen Wang , Feng-Cheng Yang , Chung-Te Lin
摘要： A memory device, a semiconductor device and manufacturing methods for forming the memory device and the semiconductor device are provided. The memory device includes a stacking structure, a switching layer, channel layers and pairs of conductive pillars. The stacking structure includes alternately stacked isolation layers and word lines, and extends along a first direction. The stacking structure has a staircase portion and a connection portion at an edge region of the stacking structure. The connection portion extends along the staircase portion and located aside the staircase portion, and may not be shaped into a staircase structure. The switching layer covers a sidewall of the stacking structure. The channel layers cover a sidewall of the switching layer, and are laterally spaced apart from one another along the first direction. The pairs of conductive pillars stand on the substrate, and in lateral contact with the switching layer through the channel layers.
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公开(公告)号：US11758734B2
公开(公告)日：2023-09-12
申请号：US17458692
申请日：2021-08-27
发明人： Peng-Chun Liou , Zhiqiang Wu , Ya-Yun Cheng , Yi-Ching Liu , Meng-Han Lin
摘要： A semiconductor device includes a first conductive structure extending along a vertical direction and a second conductive structure extending along the vertical direction. The second conductive structure is spaced apart from the first conductive structure along a first lateral direction. The semiconductor device includes third conductive structures each extending along the first lateral direction. The third conductive structures are disposed across the first and second conductive structures. The semiconductor device includes a first semiconductor channel extending along the vertical direction. The first semiconductor channel is disposed between the third conductive structures and the first conductive structure, and between the third conductive structures and the second conductive structure. The first and second conductive structures each have a first varying width along the first lateral direction, and the first semiconductor channel has a second varying width along a second lateral direction.
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公开(公告)号：US11756591B2
公开(公告)日：2023-09-12
申请号：US17460215
申请日：2021-08-28
发明人： Meng-Sheng Chang , Chia-En Huang , Yi-Ching Liu , Yih Wang
IPC分类号： G11C5/06
CPC分类号： G11C5/063
摘要： Disclosed herein are related to a memory array including a set of memory cells and a set of switches to configure the set of memory cells. In one aspect, each switch is connected between a corresponding local line and a corresponding subset of memory cells. The local clines may be connected to a global line. Local lines may be metal rails, for example, local bit lines or local select lines. A global line may be a metal rail, for example, a global bit line or a global select line. A switch may be enabled or disabled to electrically couple a controller to a selected subset of memory cells through the global line. Accordingly, the set of memory cells can be configured through the global line rather than a number of metal rails to achieve area efficiency.
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