Cargo vehicle
    31.
    发明授权
    Cargo vehicle 失效
    货车

    公开(公告)号:US4850787A

    公开(公告)日:1989-07-25

    申请号:US935307

    申请日:1986-11-26

    申请人: Takashi Yoneda

    发明人: Takashi Yoneda

    IPC分类号: B60P1/48

    CPC分类号: B60P1/483 Y10S414/13

    摘要: A cargo-work vehicle for detachably supporting a container has lift arms for rotatably supporting the container and a single cooperating auxiliary arm which ensures that the attitude of the container is held constant when the container is loaded and unloaded. A dump pin is also provided for fixing the container relative to the lift arms so that the container can be rotated relative to the vehicle body for dumping of the container load. The single auxiliary arm is advantageous because it can be located centrally of the vehicle and substantially underneath the loaded container. Such placement of the auxiliary arm affords compactness, reduces costs, and allows a single auxiliary arm to maintain the desired, constant attitude of the container during loading and unloading of the container.

    摘要翻译: 用于可拆卸地支撑容器的货物车辆具有用于可旋转地支撑容器的提升臂和单个协作辅助臂,其确保当容器被装载和卸载时容器的姿态保持恒定。 还提供了倾卸销,用于相对于提升臂固定容器,使得容器能够相对于车体旋转以倾倒容器负载。 单个辅助臂是有利的,因为它可以位于车辆的中央并且基本上位于加载的容器的下方。 辅助臂的这种布置提供了紧凑性,降低了成本,并且允许单个辅助臂在容器的装载和卸载期间保持容器所需的恒定姿态。

    METHOD FOR EVALUATION OF QUALITY OF BLOOD SAMPLE
    32.
    发明申请
    METHOD FOR EVALUATION OF QUALITY OF BLOOD SAMPLE 有权
    评估血液样品质量的方法

    公开(公告)号:US20110244476A1

    公开(公告)日:2011-10-06

    申请号:US12744064

    申请日:2008-11-25

    IPC分类号: G01N33/74 G01N33/53

    摘要: A method for evaluating the quality of a blood sample, comprising the steps of: mixing labeled anti-cortisol antibodies with a blood sample to be subjected, to conduct the antigen-antibody reaction of the labeled anti-cortisol antibody with cortisol contained in the blood sample, developing a mixture obtained in the above step on an immunochromatographic test strip having a substrate on which cortisol is immobilized to cause the antigen-antibody reaction of the labeled anti-cortisol antibodies which are free in the mixture with the cortisol immobilized on the substrate, thereby bonding the antibody to the cortisol, determining the amount of the labeled anti-cortisol antibodies bonded to the cortisol in the above step, and evaluating whether or not the blood sample has a quality suitable for suprarenal vein sampling test on the basis of the amount of the labeled anti-cortisol antibodies determined in the above step.

    摘要翻译: 一种用于评估血液样品质量的方法,包括以下步骤:将标记的抗皮质醇抗体与待进行血液样品混合,进行标记的抗皮质醇抗体与血液中包含的皮质醇的抗原 - 抗体反应 样品,将在上述步骤中获得的混合物在具有固定有皮质醇的底物的免疫色谱试纸上培养,引起与固定在底物上的皮质醇混合物中游离的标记抗皮质醇抗体的抗原 - 抗体反应 从而将抗体结合到皮质醇上,确定在上述步骤中与皮质醇结合的标记的抗皮质醇抗体的量,并且基于上述步骤评估血液样品是否具有适合于肾上静脉取样试验的质量 在上述步骤中测定的标记的抗皮质醇抗体的量。

    Method for supplying gas
    33.
    发明申请
    Method for supplying gas 有权
    供气方法

    公开(公告)号:US20110232772A1

    公开(公告)日:2011-09-29

    申请号:US12998804

    申请日:2009-12-02

    IPC分类号: F15D1/00

    摘要: [Problem] The present invention provides a gas supply method by which a gas in a gas container can be effectively utilized.[Means for Solving the Problem] On the basis of: the maximum flow rate (a first preset flow rate (Q1)) and the minimum flow rate (a second preset flow rate (Q2)) at the place where the gas is used; a first preset pressure (P1) at which the gas can be supplied at a first preset flow rate (Q1); a second preset pressure (P2) at which the gas can be supplied at a second preset flow rate (Q2); a third preset pressure (P3) which is higher than the first preset pressure (P1); residual pressures (PA, PB) in gas containers (SA, SB); a supplied gas flow rate (Q); and the relationship between the residual pressures (PA, PB) and suppliable gas flow rates (QPA and QPB, respectively), the residual pressures (PA, PB) and the supplied gas flow rate (Q) are monitored and the gas supply is switched between the first gas container (SA) and the second gas container (SB).

    摘要翻译: 本发明提供一种能够有效利用气体容器内的气体的气体供给方法。 基于:在使用气体的地方的最大流量(第一预设流量(Q1))和最小流量(第二预设流量(Q2))的基础上, 可以以第一预设流量(Q1)供应气体的第一预设压力(P1); 可以以第二预设流量(Q2)供应气体的第二预设压力(P2); 第三预设压力(P3)高于第一预设压力(P1); 气体容器(SA,SB)中的残余压力(PA,PB); 提供的气体流量(Q); 并且监测剩余压力(PA,PB)和可供应气体流量(分别为QPA和QPB),残余压力(PA,PB)和供应气体流量(Q)之间的关系,并且气体供应被切换 在第一气体容器(SA)和第二气体容器(SB)之间。

    Porphyrazine coloring matter and ink composition containing the same
    34.
    发明授权
    Porphyrazine coloring matter and ink composition containing the same 有权
    紫菜色素和含有相同成分的油墨组合物

    公开(公告)号:US07981204B2

    公开(公告)日:2011-07-19

    申请号:US12810376

    申请日:2008-12-25

    摘要: The present invention relates to a porphyrazine coloring matter represented by the following formula (1) or a salt thereof: wherein, the rings A, B, C and D shown by broken lines each independently represent a 6-membered ring having aromaticity, at least 1.0 of said rings A to D is a benzene ring and at least 0.5 of them is a nitrogen-containing heteroaromatic ring, when shown as an average value; E represents an alkylene group; X and Y are each independently an anilino group having 1 to 3 carboxy groups; and b is 0 to 3.4, c is 0.1 to 3.5, and the sum of b and c is 1.0 to 3.5, when shown as an average value. The present invention can provide a porphyrazine coloring matter suitable for inkjet recording, which has characteristics of having a good hue as cyan ink, excellent fastnesses, in particular, extremely excellent water fastness when printed on plain paper, and high solubility in water or a water-soluble organic solvent.

    摘要翻译: 本发明涉及由下式(1)表示的四氮杂卟啉色素或其盐:其中,虚线所示的环A,B,C和D各自独立地表示具有芳香性的6元环,至少 所述环A至D中的一个为苯环,当其为平均值时,其中至少0.5个为含氮杂芳族环; E表示亚烷基; X和Y各自独立地为具有1至3个羧基的苯胺基; b为0〜3.4,c为0.1〜3.5,b与c的和为平均值时为1.0〜3.5。 本发明可以提供一种适用于喷墨记录的四氮杂卟啉色素,其具有青色油墨具有良好色调的特性,优异的坚牢度,特别是在普通纸上印刷时耐水性极好,在水或水中的溶解度高 - 可溶性有机溶剂。

    LSI design method
    35.
    发明授权
    LSI design method 有权
    LSI设计方法

    公开(公告)号:US07257789B2

    公开(公告)日:2007-08-14

    申请号:US11014814

    申请日:2004-12-20

    IPC分类号: G06F17/50

    CPC分类号: G06F17/505

    摘要: An LSI design method according to the present invention is to estimate a timing uncertainty in an early stage of design for each item of which an influence on timing is uncertain among respective items requiring consideration relating to establishment of timing; and define a timing margin in each design stage by using the timing uncertainty estimation result depending on whether or not an influence of the each item on timing has been determined, followed by proceeding with the design in the respective design stages accordingly. As such, according to the present invention, a timing uncertainty is estimated in an early stage of LSI design, followed by proceeding with the design by using the timing uncertainty as required.

    摘要翻译: 根据本发明的LSI设计方法是在与设定定时有关的各个项目的各个项目中对每个项目的每个项目的时间不确定性进行估计的时间不确定性; 并且通过使用定时不确定性估计结果来确定每个设计阶段中的定时裕度,这取决于每个项目对定时的影响是否已被确定,随后在相应的设计阶段中进行设计。 因此,根据本发明,在LSI设计的早期阶段估计时序不确定度,然后根据需要使用定时不确定性进行设计。

    Semiconductor device
    36.
    发明申请
    Semiconductor device 失效
    半导体器件

    公开(公告)号:US20070127178A1

    公开(公告)日:2007-06-07

    申请号:US11606979

    申请日:2006-12-01

    申请人: Takashi Yoneda

    发明人: Takashi Yoneda

    IPC分类号: H02H3/24

    CPC分类号: G06F1/28

    摘要: A memory voltage monitoring circuit generates a low voltage detection signal when a power supply voltage drops below a memory contents holding voltage. A reset circuit generates a reset signal from an external reset signal and outputs the reset signal to the memory voltage monitoring circuit as an operation permission/no-permission signal. The memory voltage monitoring circuit operates while the reset signal shows operation permission.

    摘要翻译: 当电源电压低于存储器内容保持电压时,存储器电压监视电路产生低电压检测信号。 复位电路从外部复位信号生成复位信号,并将该复位信号作为运行允许/不允许信号输出到存储器电压监视电路。 当复位信号显示操作许可时,存储器电压监视电路工作。

    Layout analysis method and apparatus for semiconductor integrated circuit
    37.
    发明申请
    Layout analysis method and apparatus for semiconductor integrated circuit 有权
    半导体集成电路布局分析方法和装置

    公开(公告)号:US20070106967A1

    公开(公告)日:2007-05-10

    申请号:US11396660

    申请日:2006-04-04

    IPC分类号: G06F17/50

    CPC分类号: G06F17/5081

    摘要: A method for analyzing a layout for a semiconductor integrated circuit, which includes a plurality of physical devices, to generate physical parameter distribution enabling accurate recognition of changes in transistor characteristics caused by systematic variations. The method includes holding systematic variation tables for physical parameters dependent on the layout of the semiconductor integrated circuit among physical parameters related to characteristics of the semiconductor integrated circuit, analyzing a design layout pattern of the semiconductor integrated circuit and selecting tables corresponding to the plurality of physical devices, and generating a physical parameter distribution based on the selected tables.

    摘要翻译: 一种用于分析包括多个物理设备的半导体集成电路的布局的方法,用于生成物理参数分布,使得能够精确地识别由系统变化引起的晶体管特性的变化。 该方法包括:根据与半导体集成电路的特性相关的物理参数中的半导体集成电路的布局,取得物理参数的系统变化表,分析半导体集成电路的设计布局图案,以及选择与多个物理 设备,并且基于所选择的表生成物理参数分布。

    Semiconductor integrated circuit having improving program recovery capabilities
    38.
    发明授权
    Semiconductor integrated circuit having improving program recovery capabilities 有权
    具有提高程序恢复能力的半导体集成电路

    公开(公告)号:US07103738B2

    公开(公告)日:2006-09-05

    申请号:US10647260

    申请日:2003-08-26

    IPC分类号: G06F12/16 G06F12/11

    CPC分类号: G06F13/28

    摘要: A backup memory, a DMA (direct memory access) controller, and a WDT (watch dog timer) are provided in addition to a CPU (central processing unit), a RAM (random access memory), and a peripheral circuit. The DMA controller exercises control so that respective data of the CPU, RAM and peripheral circuit is saved in the backup memory each time the CPU, being under normal operation, supplies a counter reset signal to the WDT, and so that the data that has been saved in the backup memory is restored to the CPU, the RAM and the peripheral circuit, respectively, if the WDT has detected a program runaway and outputted a time-over signal. Therefore, even in a case where a program runaway has occurred in the CPU, normal operation is permitted to be resumed from midway in the program.

    摘要翻译: 除了CPU(中央处理单元),RAM(随机存取存储器)和外围电路之外,还提供备用存储器,DMA(直接存储器访问)控制器和WDT(看门狗定时器)。 DMA控制器进行控制,以使CPU,RAM和外围电路的每个数据都保存在备用存储器中,每当处于正常操作状态的CPU向WDT提供计数器复位信号时, 如果WDT检测到程序失控并输出超时信号,则保存在备份存储器中的数据被分别还原到CPU,RAM和外围电路。 因此,即使在CPU中发生程序失控的情况下,也可以在程序的中途恢复正常的动作。

    LSI design method
    39.
    发明申请
    LSI design method 有权
    LSI设计方法

    公开(公告)号:US20050278672A1

    公开(公告)日:2005-12-15

    申请号:US11014814

    申请日:2004-12-20

    CPC分类号: G06F17/505

    摘要: An LSI design method according to the present invention is to estimate a timing uncertainty in an early stage of design for each item of which an influence on timing is uncertain among respective items requiring consideration relating to establishment of timing; and define a timing margin in each design stage by using the timing uncertainty estimation result depending on whether or not an influence of the each item on timing has been determined, followed by proceeding with the design in the respective design stages accordingly. As such, according to the present invention, a timing uncertainty is estimated in an early stage of LSI design, followed by proceeding with the design by using the timing uncertainty as required.

    摘要翻译: 根据本发明的LSI设计方法是在与设定定时有关的各个项目的各个项目中对每个项目的每个项目的时间不确定性进行估计的时间不确定性; 并且通过使用定时不确定性估计结果来确定每个设计阶段中的定时裕度,这取决于每个项目对定时的影响是否已被确定,随后在相应的设计阶段中进行设计。 因此,根据本发明,在LSI设计的早期阶段估计时序不确定度,然后根据需要使用定时不确定性进行设计。

    Timing analysis apparatus, timing analysis method and program product
    40.
    发明申请
    Timing analysis apparatus, timing analysis method and program product 失效
    定时分析仪器,时序分析方法和程序产品

    公开(公告)号:US20050081171A1

    公开(公告)日:2005-04-14

    申请号:US10807286

    申请日:2004-03-24

    IPC分类号: G06F17/50 G06F9/45 H01L21/82

    CPC分类号: G06F17/5031

    摘要: OCV coefficients in a path being an analysis target according to the number of gate stages are calculated in a coefficient arithmetically operating unit by canceling off a variation in delay in each gate in accordance with the number of gate stages in the target path, and timing analysis of the target path is performed in a timing analysis unit by using the OCV coefficient with the number of gate stages being considered, whereby a variation degree in the entire path is reduced in accordance with the number of gate stages in the target path, thus making it possible to carry out accurate timing analysis in consideration of the variation in a chip of a semiconductor integrated circuit.

    摘要翻译: 根据栅极级的数量,在系数运算单元中计算作为分析对象的路径中的OCV系数,通过根据目标路径中的门级的数量消除每个门的延迟的变化,以及定时分析 通过使用考虑了门级数的OCV系数在定时分析单元中执行目标路径的变化,从而根据目标路径中的门级数减少整个路径的变化程度,从而使 考虑到半导体集成电路的芯片的变化,可以进行准确的时序分析。