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公开(公告)号：US07592684B2
公开(公告)日：2009-09-22
申请号：US11461165
申请日：2006-07-31
IPC分类号： H01L27/12
CPC分类号： H01L21/823418 , H01L21/823462
摘要： A semiconductor device is provided in which high breakdown voltage transistors and low voltage driving transistors are formed on the same substrate. The device includes a semiconductor layer, first element isolation regions for defining a high breakdown voltage transistor forming region in the semiconductor layer, second element isolation regions including trench dielectric layers for defining a low voltage driving transistor forming region in the semiconductor layer, high breakdown voltage transistors formed in the high breakdown voltage transistor forming region, low voltage driving transistors formed in the low voltage driving transistor forming region, and offset dielectric layers for alleviating the electric field of the high breakdown voltage transistors formed in the high breakdown voltage transistor forming region, wherein upper ends of the offset dielectric layers are beak shaped.
摘要翻译： 提供了一种半导体器件，其中在相同的衬底上形成有高的击穿电压晶体管和低电压驱动晶体管。 所述器件包括半导体层，用于限定半导体层中的高击穿电压晶体管形成区域的第一元件隔离区域，包括用于限定半导体层中的低电压驱动晶体管形成区域的沟槽电介质层的第二元件隔离区域，高击穿电压 形成在高击穿电压晶体管形成区域中的晶体管，形成在低电压驱动晶体管形成区域中的低电压驱动晶体管，以及用于减轻形成在高击穿电压晶体管形成区域中的高击穿电压晶体管的电场的偏移电介质层， 其中偏移电介质层的上端为喙状。
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公开(公告)号：US07507622B2
公开(公告)日：2009-03-24
申请号：US11294801
申请日：2005-12-06
申请人： Takafumi Noda , Masahiro Hayashi
发明人： Takafumi Noda , Masahiro Hayashi
IPC分类号： H01L21/8242
CPC分类号： H01L29/0619 , H01L29/0653 , H01L29/0692 , H01L29/7833
摘要： A semiconductor device includes a semiconductor layer, an insulated-gate field effect transistor provided in the semiconductor layer, an etching stopper film provided above the insulated-gate field effect transistor, and an interlayer insulating layer provided above the etching stopper film; the insulated-gate field effect transistor including a gate insulating layer provided on the semiconductor layer, a gate electrode provided on the gate insulating layer, and an impurity region that constitutes a source region or a drain region provided in the semiconductor layer; wherein a removed region made by removing the etching stopper film is provided in at least part of an area that is located outside the gate insulating layer and above an area at a position other than a position sandwiched by the gate insulating layer and the impurity region.
摘要翻译： 半导体器件包括半导体层，设置在半导体层中的绝缘栅场效应晶体管，设置在绝缘栅场效应晶体管上方的蚀刻阻挡膜，以及设置在蚀刻阻挡膜上方的层间绝缘层; 所述绝缘栅场效应晶体管包括设置在所述半导体层上的栅极绝缘层，设置在所述栅极绝缘层上的栅极电极和构成设置在所述半导体层中的源极区域或漏极区域的杂质区域; 其中，通过去除蚀刻阻挡膜而形成的去除区域设置在位于栅极绝缘层外部的区域的至少一部分上方，并且位于除了被栅极绝缘层和杂质区域夹持的位置以外的位置的区域的上方。
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公开(公告)号：US20090072286A1
公开(公告)日：2009-03-19
申请号：US12171590
申请日：2008-07-11
申请人： Takafumi Noda
发明人： Takafumi Noda
CPC分类号： H01L27/11507 , H01L21/76804 , H01L21/76816 , H01L21/76897 , H01L27/11502 , H01L28/55 , H01L28/57
摘要： A semiconductor device includes: a ferroelectric capacitor that is provided above a base substrate and includes a first electrode, a ferroelectric film provided on the first electrode and a second electrode provided on the ferroelectric film; a stopper film that covers a top surface of the second electrode of the ferroelectric capacitor; a hydrogen barrier film that covers a top surface and a side surface of the stopper film and a side surface of the ferroelectric capacitor; an interlayer dielectric film that covers the hydrogen barrier film and the base substrate; a contact hole that penetrates the interlayer dielectric film, the hydrogen barrier film and the stopper film and exposes the second electrode; a barrier metal that covers the second electrode exposed in the contact hole and an inner wall surface of the contact hole and is composed of a conductive material having hydrogen barrier property; and a plug conductive section that is embedded in the contact hole and conductively connects to the barrier metal, wherein the stopper film is formed from a dielectric material having a smaller etching rate than an etching rate of the interlayer dielectric film.
摘要翻译： 半导体器件包括：设置在基底基板上方的铁电电容器，具有第一电极，设置在第一电极上的铁电体膜和设置在强电介质膜上的第二电极; 覆盖所述强电介质电容器的第二电极的顶面的阻挡膜; 覆盖所述阻挡膜的顶面和侧面以及所述强电介质电容器的侧面的氢阻挡膜; 覆盖所述氢阻挡膜和所述基底基板的层间绝缘膜; 穿过层间电介质膜的接触孔，氢阻挡膜和阻挡膜，暴露第二电极; 覆盖在接触孔中露出的第二电极和接触孔的内壁面的阻挡金属，由具有氢阻挡性的导电材料构成; 以及嵌入在所述接触孔中并导电连接到所述阻挡金属的插塞导电部，其中所述阻挡膜由具有比所述层间绝缘膜的蚀刻速率小的蚀刻速率的电介质材料形成。
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公开(公告)号：US20050045983A1
公开(公告)日：2005-03-03
申请号：US10899298
申请日：2004-07-26
IPC分类号： H01L21/76 , H01L21/762 , H01L21/8234 , H01L21/8238 , H01L27/088 , H01L27/092 , H01L29/00
CPC分类号： H01L21/823481 , H01L21/76229 , H01L21/823462
摘要： A semiconductor device is provided that includes a semiconductor layer, first element isolation regions defining a high breakdown voltage transistor forming region in the semiconductor layer, second element isolation regions defining a low voltage driving transistor forming region in the semiconductor layer, high breakdown voltage transistors formed in the high breakdown voltage transistor forming region, low voltage driving transistors formed in the low voltage driving transistor forming region, and offset dielectric layers for alleviating an electric field of the high breakdown voltage transistors, wherein the high breakdown voltage transistors have gate dielectric layers formed by a CVD method.
摘要翻译： 提供一种半导体器件，其包括半导体层，在半导体层中限定高击穿电压晶体管形成区域的第一元件隔离区域，限定半导体层中的低电压驱动晶体管形成区域的第二元件隔离区域，形成的高击穿电压晶体管 在高击穿电压晶体管形成区域中，形成在低电压驱动晶体管形成区域中的低电压驱动晶体管，以及用于减轻高击穿电压晶体管的电场的偏移电介质层，其中高击穿电压晶体管形成栅极电介质层 通过CVD法。
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公开(公告)号：US06713886B2
公开(公告)日：2004-03-30
申请号：US09827391
申请日：2001-04-06
IPC分类号： H01L2711
CPC分类号： H01L27/1104
摘要： A semiconductor device includes an SRAM section and a logic circuit section formed on a single semiconductor substrate. First and second gate electrode layers located in a first conductive layer, first and second drain-drain contact layers located in a second conductive layer, first and second drain-gate contact layers located in a third conductive layer become conductive layers for forming a flip-flop of the SRAM section. The logic circuit section has no wiring layer at the same level as the first and second drain-drain contact layers.
摘要翻译： 半导体器件包括形成在单个半导体衬底上的SRAM部分和逻辑电路部分。 位于第一导电层中的第一和第二栅极电极层，位于第二导电层中的第一和第二漏极 - 漏极接触层，位于第三导电层中的第一和第二漏极 - 栅极接触层变成导电层， 的SRAM部分。 逻辑电路部分没有与第一和第二漏极 - 漏极接触层处于相同电平的布线层。
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36.发明授权Semiconductor memory device having improved pattern of layers and compact dimensions 失效半导体存储器件具有改进的层的图案和紧凑的尺寸公开(公告)号：US06455899B2
公开(公告)日：2002-09-24
申请号：US09764449
申请日：2001-01-19
IPC分类号： H01L2976
CPC分类号： G11C11/412 , Y10S257/903
摘要： First and second gate electrode layers that are positioned in a first conductive layer, first and second drain-drain contact layers that are positioned in a second conductive layer, and first and second drain-gate contact layers that are positioned in a third conductive layer together form conductive layers for a flip-flop. A sub word line extends in the X-axis direction in the first conductive layer. A VDD wire is disposed extending in the X-axis direction in the second conductive layer. A main word line is disposed extending in the X-axis direction in the third conductive layer. A bit line, a bit line/, a VSS wire, and a VDD wire are disposed extending in the Y-axis direction in the fourth conductive layer.
摘要翻译： 位于第一导电层中的第一和第二栅极电极层，位于第二导电层中的第一和第二漏极 - 漏极接触层以及位于第三导电层中的第一和第二漏极 - 栅极接触层 形成触发器的导电层。 子字线在第一导电层中在X轴方向上延伸。 在第二导电层中，在X轴方向上配置VDD线。 主字线在第三导电层中在X轴方向上延伸设置。 在第四导电层中沿Y轴方向延伸有位线，位线/ VSS线和VDD线。
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37.发明授权Semiconductor memory device having gate electrode, drain-drain contact, and drain-gate contact layers 失效具有栅电极，漏极 - 漏极接触和漏极 - 栅极接触层的半导体存储器件公开(公告)号：US06407463B2
公开(公告)日：2002-06-18
申请号：US09736386
申请日：2000-12-15
IPC分类号： H01L2711
CPC分类号： H01L27/1104
摘要： The drain of a drive transistor Q3 and the drain of a load transistor Q5 are connected by a first drain—drain contact layer. The drain of a drive transistor Q4 and the drain of a load transistor Q6 are connected by a second drain—drain contact layer. The gate electrodes of the drive transistor Q3 and the load transistor Q5 (a first gate electrode layer) are connected to the second drain—drain contact layer by a first drain-gate contact layer. The gate electrodes of the drive transistor Q4 and the load transistor Q6 (a second gate electrode layer) are connected to the first drain—drain contact layer by a second drain-gate contact layer.
摘要翻译： 驱动晶体管Q3的漏极和负载晶体管Q5的漏极通过第一漏极 - 漏极接触层连接。 驱动晶体管Q4的漏极和负载晶体管Q6的漏极通过第二漏极 - 漏极接触层连接。 驱动晶体管Q3和负载晶体管Q5（第一栅极电极层）的栅电极通过第一漏极 - 栅极接触层连接到第二漏极 - 漏极接触层。 驱动晶体管Q4的栅电极和负载晶体管Q6（第二栅极电极层）通过第二漏极 - 栅极接触层连接到第一漏极 - 漏极接触层。
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公开(公告)号：US06347048B2
公开(公告)日：2002-02-12
申请号：US09841105
申请日：2001-04-25
IPC分类号： G11C1100
CPC分类号： H01L27/1104 , Y10S257/903
摘要： A semiconductor memory device comprising first and second gate electrode layers in a first conductive layer, first and second drain-drain connecting layers in a second conductive layer, and first and second drain-gate connecting layers in a third conductive layer. The first and second drain-gate connecting layers are located higher than the first and second gate electrode layers. Therefore, a source contact layer can be located in the region between gate electrode layers while preventing a contact with the second drain-gate connecting layer.
摘要翻译： 一种半导体存储器件，包括在第一导电层中的第一和第二栅极电极层，第二导电层中的第一和第二漏极 - 漏极连接层，以及第三导电层中的第一和第二漏极 - 栅极连接层。 第一和第二漏极 - 栅极连接层位于比第一和第二栅极电极层高的位置。 因此，源极接触层可以位于栅极电极层之间的区域中，同时防止与第二漏极 - 栅极连接层的接触。
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公开(公告)号：US09182288B2
公开(公告)日：2015-11-10
申请号：US13069843
申请日：2011-03-23
申请人： Takafumi Noda , Jun Takizawa
发明人： Takafumi Noda , Jun Takizawa
摘要： A thermal detector includes a thermal detection element, a support member, and a fixing part supporting the support member. The support member mounts and supports the thermal detection element on a second side thereof with a first side thereof facing a cavity. The support member includes a first layer member disposed on the second side and having a residual stress in a first direction, and a second layer member laminated on the first layer member on the first side and having a residual stress in a second direction opposite to the first direction. A thermal conductance of the first layer member is less than a thermal conductance of the second layer member.
摘要翻译： 热检测器包括热检测元件，支撑构件和支撑支撑构件的固定部。 支撑构件在其第二侧上安装和支撑热检测元件，其第一侧面向空腔。 支撑构件包括设置在第二侧上并且在第一方向上具有残余应力的第一层构件和在第一侧上层叠在第一层构件上并且在与第一侧相反的第二方向上具有残余应力的第二层构件 第一个方向 第一层构件的热导率小于第二层构件的热导率。
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公开(公告)号：US09163993B2
公开(公告)日：2015-10-20
申请号：US13371679
申请日：2012-02-13
申请人： Takafumi Noda
发明人： Takafumi Noda
CPC分类号： G01J5/0025 , G01J5/023 , G01J5/0235 , G01J5/024 , G01J5/0896 , G01J5/20
摘要： A thermal detector includes a substrate, a support member, a spacer member, a thermal detection element, a detection circuit and a wiring part. The spacer member supports the support member over the substrate with a cavity part being formed therebetween. The thermal detection element is supported on the support member. The wiring part connects between the detection circuit and the thermal detection element, and has first through third conductive layer parts and a plurality of plugs. The first conductive layer part includes at least one layer disposed in the substrate. The second conductive layer part includes at least one layer disposed in the spacer member. The third conductive layer part includes at least one layer supported by the support member. The plugs respectively connect adjacent layers of the first conductive layer part, the second conductive layer part and the third conductive layer part, in a thickness direction of the substrate.
摘要翻译： 热检测器包括基板，支撑构件，间隔构件，热检测元件，检测电路和布线部。 隔离构件在衬底上支撑支撑构件，其间形成有空腔部分。 热检测元件支撑在支撑构件上。 布线部分连接在检测电路和热检测元件之间，并且具有第一至第三导电层部分和多个插塞。 第一导电层部分包括设置在基板中的至少一层。 第二导电层部分包括设置在间隔件中的至少一层。 第三导电层部分包括由支撑构件支撑的至少一层。 插头分别在基板的厚度方向上连接第一导电层部分，第二导电层部分和第三导电层部分的相邻层。
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