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公开(公告)号：US20060163623A1
公开(公告)日：2006-07-27
申请号：US11294801
申请日：2005-12-06
申请人： Takafumi Noda , Masahiro Hayashi
发明人： Takafumi Noda , Masahiro Hayashi
IPC分类号： H01L29/76
CPC分类号： H01L29/0619 , H01L29/0653 , H01L29/0692 , H01L29/7833
摘要： A semiconductor device includes a semiconductor layer, an insulated-gate field effect transistor provided in the semiconductor layer, an etching stopper film provided above the insulated-gate field effect transistor, and an interlayer insulating layer provided above the etching stopper film; the insulated-gate field effect transistor including a gate insulating layer provided on the semiconductor layer, a gate electrode provided on the gate insulating layer, and an impurity region that constitutes a source region or a drain region provided in the semiconductor layer; wherein a removed region made by removing the etching stopper film is provided in at least part of an area that is located outside the gate insulating layer and above an area at a position other than a position sandwiched by the gate insulating layer and the impurity region.
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公开(公告)号：US07592684B2
公开(公告)日：2009-09-22
申请号：US11461165
申请日：2006-07-31
IPC分类号： H01L27/12
CPC分类号： H01L21/823418 , H01L21/823462
摘要： A semiconductor device is provided in which high breakdown voltage transistors and low voltage driving transistors are formed on the same substrate. The device includes a semiconductor layer, first element isolation regions for defining a high breakdown voltage transistor forming region in the semiconductor layer, second element isolation regions including trench dielectric layers for defining a low voltage driving transistor forming region in the semiconductor layer, high breakdown voltage transistors formed in the high breakdown voltage transistor forming region, low voltage driving transistors formed in the low voltage driving transistor forming region, and offset dielectric layers for alleviating the electric field of the high breakdown voltage transistors formed in the high breakdown voltage transistor forming region, wherein upper ends of the offset dielectric layers are beak shaped.
摘要翻译： 提供了一种半导体器件，其中在相同的衬底上形成有高的击穿电压晶体管和低电压驱动晶体管。 所述器件包括半导体层，用于限定半导体层中的高击穿电压晶体管形成区域的第一元件隔离区域，包括用于限定半导体层中的低电压驱动晶体管形成区域的沟槽电介质层的第二元件隔离区域，高击穿电压 形成在高击穿电压晶体管形成区域中的晶体管，形成在低电压驱动晶体管形成区域中的低电压驱动晶体管，以及用于减轻形成在高击穿电压晶体管形成区域中的高击穿电压晶体管的电场的偏移电介质层， 其中偏移电介质层的上端为喙状。
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公开(公告)号：US07507622B2
公开(公告)日：2009-03-24
申请号：US11294801
申请日：2005-12-06
申请人： Takafumi Noda , Masahiro Hayashi
发明人： Takafumi Noda , Masahiro Hayashi
IPC分类号： H01L21/8242
CPC分类号： H01L29/0619 , H01L29/0653 , H01L29/0692 , H01L29/7833
摘要： A semiconductor device includes a semiconductor layer, an insulated-gate field effect transistor provided in the semiconductor layer, an etching stopper film provided above the insulated-gate field effect transistor, and an interlayer insulating layer provided above the etching stopper film; the insulated-gate field effect transistor including a gate insulating layer provided on the semiconductor layer, a gate electrode provided on the gate insulating layer, and an impurity region that constitutes a source region or a drain region provided in the semiconductor layer; wherein a removed region made by removing the etching stopper film is provided in at least part of an area that is located outside the gate insulating layer and above an area at a position other than a position sandwiched by the gate insulating layer and the impurity region.
摘要翻译： 半导体器件包括半导体层，设置在半导体层中的绝缘栅场效应晶体管，设置在绝缘栅场效应晶体管上方的蚀刻阻挡膜，以及设置在蚀刻阻挡膜上方的层间绝缘层; 所述绝缘栅场效应晶体管包括设置在所述半导体层上的栅极绝缘层，设置在所述栅极绝缘层上的栅极电极和构成设置在所述半导体层中的源极区域或漏极区域的杂质区域; 其中，通过去除蚀刻阻挡膜而形成的去除区域设置在位于栅极绝缘层外部的区域的至少一部分上方，并且位于除了被栅极绝缘层和杂质区域夹持的位置以外的位置的区域的上方。
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公开(公告)号：US20050045983A1
公开(公告)日：2005-03-03
申请号：US10899298
申请日：2004-07-26
IPC分类号： H01L21/76 , H01L21/762 , H01L21/8234 , H01L21/8238 , H01L27/088 , H01L27/092 , H01L29/00
CPC分类号： H01L21/823481 , H01L21/76229 , H01L21/823462
摘要： A semiconductor device is provided that includes a semiconductor layer, first element isolation regions defining a high breakdown voltage transistor forming region in the semiconductor layer, second element isolation regions defining a low voltage driving transistor forming region in the semiconductor layer, high breakdown voltage transistors formed in the high breakdown voltage transistor forming region, low voltage driving transistors formed in the low voltage driving transistor forming region, and offset dielectric layers for alleviating an electric field of the high breakdown voltage transistors, wherein the high breakdown voltage transistors have gate dielectric layers formed by a CVD method.
摘要翻译： 提供一种半导体器件，其包括半导体层，在半导体层中限定高击穿电压晶体管形成区域的第一元件隔离区域，限定半导体层中的低电压驱动晶体管形成区域的第二元件隔离区域，形成的高击穿电压晶体管 在高击穿电压晶体管形成区域中，形成在低电压驱动晶体管形成区域中的低电压驱动晶体管，以及用于减轻高击穿电压晶体管的电场的偏移电介质层，其中高击穿电压晶体管形成栅极电介质层 通过CVD法。
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公开(公告)号：US07163855B2
公开(公告)日：2007-01-16
申请号：US10902699
申请日：2004-07-29
IPC分类号： H01L21/336 , H01L21/8238 , H01L21/8234
CPC分类号： H01L21/823892 , H01L21/823814 , H01L21/823857 , H01L27/0922 , H01L27/0928
摘要： A semiconductor device manufacturing method is provided including: forming a first impurity layer that becomes first wells in a high breakdown voltage transistor forming region in a semiconductor layer; forming a second impurity layer that becomes offset regions in the high breakdown voltage transistor forming region; forming the first wells and the offset regions by diffusing impurities of the first and second impurity layers by heat treating the semiconductor layer; forming element isolation regions by a trench element isolation method in the semiconductor layer, after forming the first wells and the offset regions; forming first gate dielectric layers in the high breakdown voltage transistor forming region; forming second wells in a low voltage driving transistor forming region in the semiconductor layer; forming second gate dielectric layers in the low voltage driving transistor forming region; and forming gate electrodes in the high breakdown voltage transistor forming region and the low voltage driving transistor forming region.
摘要翻译： 提供一种半导体器件制造方法，包括：在半导体层中形成在高击穿电压晶体管形成区域中成为第一阱的第一杂质层; 形成成为所述高击穿电压晶体管形成区域的偏移区域的第二杂质层; 通过热处理所述半导体层来扩散所述第一和第二杂质层的杂质来形成所述第一阱和所述偏移区域; 在形成第一阱和偏移区之后，通过沟槽元件隔离方法在半导体层中形成元件隔离区; 在高击穿电压晶体管形成区域中形成第一栅极电介质层; 在半导体层中的低电压驱动晶体管形成区域中形成第二阱; 在所述低电压驱动晶体管形成区域中形成第二栅极电介质层; 以及在高击穿电压晶体管形成区域和低电压驱动晶体管形成区域中形成栅电极。
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公开(公告)号：US07141862B2
公开(公告)日：2006-11-28
申请号：US10890403
申请日：2004-07-13
IPC分类号： H01L29/00
CPC分类号： H01L21/823418 , H01L21/823462
摘要： A semiconductor device is provided in which high breakdown voltage transistors and low voltage driving transistors are formed on the same substrate. The device includes a semiconductor layer, first element isolation regions for defining a high breakdown voltage transistor forming region in the semiconductor layer, second element isolation regions including trench dielectric layers for defining a low voltage driving transistor forming region in the semiconductor layer, high breakdown voltage transistors formed in the high breakdown voltage transistor forming region, low voltage driving transistors formed in the low voltage driving transistor forming region, and offset dielectric layers for alleviating the electric field of the high breakdown voltage transistors formed in the high breakdown voltage transistor forming region, wherein upper ends of the offset dielectric layers are beak shaped.
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公开(公告)号：US20050087835A1
公开(公告)日：2005-04-28
申请号：US10961769
申请日：2004-10-07
申请人： Masahiro Hayashi , Takafumi Noda , Yoshinobu Yusa
发明人： Masahiro Hayashi , Takafumi Noda , Yoshinobu Yusa
IPC分类号： H01L21/316 , H01L21/76 , H01L21/762 , H01L21/8234 , H01L27/08 , H01L27/088 , H01L29/78 , H01L29/00
CPC分类号： H01L21/823456 , H01L21/76202 , H01L21/76224 , H01L21/823418 , H01L21/823462 , H01L27/088
摘要： A semiconductor device of the present invention is provided with a high breakdown voltage transistor 100 and a low voltage driving transistor 200 on a same semiconductor layer 10 comprising: the semiconductor layer 10; an offset insulating layer 20 comprising a LOCOS layer for an electric field relaxation of the high breakdown voltage transistor 100 provided on the semiconductor layer 10; and a trench insulating layer 28 for defining a forming region of the low voltage driving transistor 200 provided on the semiconductor layer 10, wherein at least a part of the upper surface of the offset insulating layer 20 is nearly as high as the surface of the semiconductor layer 10.
摘要翻译： 本发明的半导体器件在同一半导体层10上设置有高耐压晶体管100和低电压驱动晶体管200，该半导体层10包括：半导体层10; 偏移绝缘层20，包括用于设置在半导体层10上的高击穿电压晶体管100的电场弛豫的LOCOS层; 以及用于限定设置在半导体层10上的低电压驱动晶体管200的形成区域的沟槽绝缘层28，其中，偏移绝缘层20的上表面的至少一部分几乎与半导体的表面一样高 第10层。
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公开(公告)号：US20050059196A1
公开(公告)日：2005-03-17
申请号：US10902699
申请日：2004-07-29
IPC分类号： H01L21/76 , H01L21/336 , H01L21/8234 , H01L21/8238 , H01L27/08 , H01L27/088 , H01L27/092
CPC分类号： H01L21/823892 , H01L21/823814 , H01L21/823857 , H01L27/0922 , H01L27/0928
摘要： A semiconductor device manufacturing method is provided including: forming a first impurity layer that becomes first wells in a high breakdown voltage transistor forming region in a semiconductor layer; forming a second impurity layer that becomes offset regions in the high breakdown voltage transistor forming region; forming the first wells and the offset regions by diffusing impurities of the first and second impurity layers by heat treating the semiconductor layer; forming element isolation regions by a trench element isolation method in the semiconductor layer, after forming the first wells and the offset regions; forming first gate dielectric layers in the high breakdown voltage transistor forming region; forming second wells in a low voltage driving transistor forming region in the semiconductor layer; forming second gate dielectric layers in the low voltage driving transistor forming region; and forming gate electrodes in the high breakdown voltage transistor forming region and the low voltage driving transistor forming region.
摘要翻译： 提供一种半导体器件制造方法，包括：在半导体层中形成在高击穿电压晶体管形成区域中成为第一阱的第一杂质层; 形成成为所述高击穿电压晶体管形成区域的偏移区域的第二杂质层; 通过热处理所述半导体层来扩散所述第一和第二杂质层的杂质来形成所述第一阱和所述偏移区域; 在形成第一阱和偏移区之后，通过沟槽元件隔离方法在半导体层中形成元件隔离区; 在高击穿电压晶体管形成区域中形成第一栅极电介质层; 在半导体层中的低电压驱动晶体管形成区域中形成第二阱; 在所述低电压驱动晶体管形成区域中形成第二栅极电介质层; 以及在高击穿电压晶体管形成区域和低电压驱动晶体管形成区域中形成栅电极。
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公开(公告)号：US20050029616A1
公开(公告)日：2005-02-10
申请号：US10890403
申请日：2004-07-13
IPC分类号： H01L21/8234 , H01L27/088 , H01L29/78 , H01L21/336 , H01L29/00
CPC分类号： H01L21/823418 , H01L21/823462
摘要： A semiconductor device is provided in which high breakdown voltage transistors and low voltage driving transistors are formed on the same substrate. The device includes a semiconductor layer, first element isolation regions for defining a high breakdown voltage transistor forming region in the semiconductor layer, second element isolation regions including trench dielectric layers for defining a low voltage driving transistor forming region in the semiconductor layer, high breakdown voltage transistors formed in the high breakdown voltage transistor forming region, low voltage driving transistors formed in the low voltage driving transistor forming region, and offset dielectric layers for alleviating the electric field of the high breakdown voltage transistors formed in the high breakdown voltage transistor forming region, wherein upper ends of the offset dielectric layers are beak shaped.
摘要翻译： 提供了一种半导体器件，其中在相同的衬底上形成有高的击穿电压晶体管和低电压驱动晶体管。 所述器件包括半导体层，用于限定半导体层中的高击穿电压晶体管形成区域的第一元件隔离区域，包括用于限定半导体层中的低电压驱动晶体管形成区域的沟槽电介质层的第二元件隔离区域，高击穿电压 形成在高击穿电压晶体管形成区域中的晶体管，形成在低电压驱动晶体管形成区域中的低电压驱动晶体管，以及用于减轻形成在高击穿电压晶体管形成区域中的高击穿电压晶体管的电场的偏移电介质层， 其中偏移电介质层的上端为喙状。
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公开(公告)号：US20130309772A1
公开(公告)日：2013-11-21
申请号：US13877225
申请日：2011-09-30
申请人： Keishi Sakaguchi , Rie Hamaguchi , Takanori Matsuda , Makoto Ito , Naoki Nagano , Masahiro Hayashi , Daisuke Honda , Yuji Okita , Shinichi Sugimoto
发明人： Keishi Sakaguchi , Rie Hamaguchi , Takanori Matsuda , Makoto Ito , Naoki Nagano , Masahiro Hayashi , Daisuke Honda , Yuji Okita , Shinichi Sugimoto
CPC分类号： C12N15/79 , C12N9/0071 , C12N9/0083 , C12N9/1029 , C12N15/113 , C12N15/52 , C12N15/895 , C12N2310/11 , C12N2310/14 , C12P7/6409 , C12P7/6427 , C12P7/6472 , C12Y114/19001 , C12Y114/19006 , C12Y203/01119
摘要： To provide a transformation method for producing a stramenopile organism having an improved unsaturated fatty acid production capability by disrupting a gene of the stramenopile organism or inhibiting the expression of the gene in a genetically engineering manner. [Solution] A method for transforming a stramenopile organism, which comprises disrupting a gene of the stramenopile organism or inhibiting the expression of the gene in a genetically engineering manner, and which is characterized in that the stramenopile organism is selected from Thraustochytrium aureum, Parietichytrium sarkarianum, Thraustochytrium roseum and Parietichytrium sp. and the gene to be disrupted or of which the expression is to be inhibited is a gene associated with the biosynthesis of a fatty acid.
摘要翻译： 提供通过以遗传工程方式破坏该层状生物体的基因或抑制该基因的表达来生产具有改善的不饱和脂肪酸生产能力的前烧石生物的转化方法。 [解决方案]一种转基因生物的方法，其包括以基因工程方式破坏所述地精生物体的基因或抑制所述基因的表达，其特征在于，所述前列腺生物体选自甲状腺破囊壶菌（Salisochytrium aureum），，鱼（Parietichytrium sarkarianum） ，玫瑰色胸，和Parietichytrium sp。 并且待破坏的基因或其表达被抑制的基因是与脂肪酸的生物合成相关的基因。
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