公开(公告)号：US06621860B1

公开(公告)日：2003-09-16

申请号：US09246458

申请日：1999-02-08

申请人： Takahiro Yamaguchi ,  Masahiro Ishida ,  Mani Soma

发明人： Takahiro Yamaguchi ,  Masahiro Ishida ,  Mani Soma

IPC分类号： H04B346

CPC分类号： G01R29/26

摘要： There is provided an apparatus for and a method of measuring a jitter wherein a clock waveform XC(t) is transformed into an analytic signal using Hilbert transform and a varying term &Dgr;&phgr;(t) of an instantaneous phase of this analytic signal is estimated.

摘要翻译： 提供了一种用于测量抖动的装置和方法，其中使用希尔伯特变换将时钟波形XC（t）变换成分析信号，并且估计该分析信号的瞬时相位的变化项DELTA（t）。

公开(公告)号：US06423558B1

公开(公告)日：2002-07-23

申请号：US09512780

申请日：2000-02-25

申请人： Yasuhiro Maeda ,  Masahiro Ishida ,  Takahiro Yamaguchi ,  Mani Soma

发明人： Yasuhiro Maeda ,  Masahiro Ishida ,  Takahiro Yamaguchi ,  Mani Soma

IPC分类号： G01R3126

CPC分类号： H01L22/20 ,  H01L2924/0002 ,  H01L2924/00

摘要： In a method for fabricating an LSI in which primitive devices such as transistors are formed on a semiconductor substrate and a plurality of interconnect layers are formed thereover to provide sub-circuits of successively larger scale and increasing complexity including sub-circuits which are formed by a connection of the primitive devices and sub-circuits of a larger scale which are formed by a connection of the sub-circuits, under a condition that an intermediate interconnect layer is formed, an exhaustive test, a functional test, a stuck-at fault test, a quiescent power supply current test or the like takes place with respect to the primitive devices or the sub-circuits which are wired together by the intermediate interconnect layer, and subsequently, a wiring connection test takes place after the formation of each subsequent interconnect layer. A fault coverage is improved while a testing cost and a fabricating cost are reduced.

摘要翻译： 在制造LSI的方法中，其中在半导体衬底上形成诸如晶体管的基本器件，并在其上形成多个互连层，以提供连续更大规模的子电路和增加复杂性的子电路，包括由 在形成中间互连层的条件下，通过子电路的连接形成的较大规模的原始器件和子电路的连接，穷举测试，功能测试，卡入故障测试 ，相对于通过中间互连层连接在一起的原始器件或子电路进行静态电源电流测试等，随后在形成每个后续互连层之后进行布线连接测试 。 提高了故障覆盖率，同时降低了测试成本和制造成本。

公开(公告)号：US06291979B1

公开(公告)日：2001-09-18

申请号：US09251096

申请日：1999-02-16

申请人： Mani Soma ,  Takahiro Yamaguchi ,  Masahiro Ishida

发明人： Mani Soma ,  Takahiro Yamaguchi ,  Masahiro Ishida

IPC分类号： G01R2500

CPC分类号： G01R31/2839 ,  G01R25/00 ,  G01R31/3016

摘要： There is provided a method of and an apparatus for detecting delay faults in phase-locked loop circuits. A frequency impulse is applied to a phase-locked loop circuit under test as the reference clock, and a waveform of a signal outputted from the phase-locked loop circuit under test is transformed to an analytic signal to estimate an instantaneous phase of the analytic signal. A linear phase is estimated from the estimated instantaneous phase, and the estimated linear phase is removed from the estimated instantaneous phase to obtain a fluctuation term of the instantaneous phase. A delay time is measured from this fluctuation term of the instantaneous phase, and further, a delay fault is detected by comparing a time duration during which the phase-locked loop circuit remains in a state of oscillating a certain frequency with a time duration during which a fault-free phase-locked loop circuit remains in a state of oscillating that certain frequency.

摘要翻译： 提供了一种用于检测锁相环电路中的延迟故障的方法和装置。 对被测定的锁相环电路施加频率脉冲作为基准时钟，将从被测锁相环电路输出的信号的波形变换成分析信号，估计分析信号的瞬时相位 。 从估计的瞬时相位估计线性相位，并且从估计的瞬时相位去除估计的线性相位以获得瞬时相位的波动项。 从瞬时相位的波动项测量延迟时间，此外，通过比较锁相环电路保持在某一频率的振荡状态的持续时间与其中的持续时间的时间间隔来检测延迟故障 无故障的锁相环电路保持在某一频率的振荡状态。

公开(公告)号：US07957458B2

公开(公告)日：2011-06-07

申请号：US11378407

申请日：2006-03-17

申请人： Kiyotaka Ichiyama ,  Masahiro Ishida ,  Takahiro Yamaguchi ,  Mani Soma

发明人： Kiyotaka Ichiyama ,  Masahiro Ishida ,  Takahiro Yamaguchi ,  Mani Soma

IPC分类号： H04Q1/20

CPC分类号： H04B17/364

摘要： A jitter measuring apparatus measures timing jitter of a signal-under-test. The jitter measuring apparatus includes a pulse generator for outputting a pulse signal of a predetermined pulse width for an edge of the signal-under-test, and a jitter measuring sub-unit for extracting the timing jitter on the basis of a duty ratio of each cycle of the signal output by the pulse generator.

摘要翻译： 抖动测量装置测量待测信号的定时抖动。 抖动测量装置包括脉冲发生器，用于输出针对待测信号的边缘的预定脉冲宽度的脉冲信号，以及抖动测量子单元，用于根据每个的占空比提取定时抖动 由脉冲发生器输出的信号周期。

公开(公告)号：US07564897B2

公开(公告)日：2009-07-21

申请号：US10896751

申请日：2004-07-22

申请人： Kiyotaka Ichiyama ,  Masahiro Ishida ,  Takahiro Yamaguchi ,  Mani Soma

发明人： Kiyotaka Ichiyama ,  Masahiro Ishida ,  Takahiro Yamaguchi ,  Mani Soma

IPC分类号： H04B3/46

CPC分类号： G01R31/31709 ,  G01R29/26 ,  G01R31/3016 ,  G01R31/31725 ,  G01R31/3191 ,  G01R31/31937

摘要： A jitter measurement apparatus for measuring an intrinsic jitter of a circuit to be tested including a phase detector which outputs a signal according to a phase difference between a supplied first input signal and a supplied second input signal, includes: an input unit for supplying an identical signal to the phase detector as the first input signal and as the second input signal; and a jitter measurement unit for measuring the intrinsic jitter of the circuit to be tested by measuring a jitter of a signal which is generated in an inside of the circuit to be tested according to an signal output from the phase detector.

摘要翻译： 一种用于测量被测电路的固有抖动的抖动测量装置，包括：根据所提供的第一输入信号和所提供的第二输入信号之间的相位差输出信号的相位检测器，包括：输入单元，用于提供相同的 向相位检测器发信号作为第一输入信号，并作为第二输入信号; 以及抖动测量单元，用于根据从相位检测器输出的信号测量待测电路的内部产生的信号的抖动来测量待测电路的固有抖动。

公开(公告)号：US07305025B2

公开(公告)日：2007-12-04

申请号：US10925870

申请日：2004-08-25

申请人： Takahiro Yamaguchi ,  Masahiro Ishida ,  Mani Soma

发明人： Takahiro Yamaguchi ,  Masahiro Ishida ,  Mani Soma

IPC分类号： H04B3/46

CPC分类号： G01R31/31709 ,  G01R29/02 ,  G01R29/0273 ,  G01R29/26 ,  G01R31/31922 ,  G01R31/31937 ,  H04L1/203 ,  H04L1/205

摘要： A measuring apparatus for measuring reliability against jitter of an electronic device, including: a jitter tolerance estimator operable to estimate a jitter tolerance of the electronic device based on an output signal output from the electronic device according to an input signal input through a transmission line of which the transmission length is shorter than a predetermined length so that it does not generate a deterministic jitter; a jitter tolerance degradation quantity estimator operable to estimate a quantity of degradation of the jitter tolerance which deteriorates by the deterministic jitter caused in the input signal by transmission through the long transmission line when the input signal is input into the electronic device through the transmission line, of which the transmission length is longer than a predetermined length so that it may cause the deterministic jitter; a system jitter tolerance estimator operable to estimate a jitter tolerance of the electronic device and a jitter tolerance of a system including the long transmission line and the electronic device based on quantity of degradation of the jitter tolerance, is provided.

摘要翻译： 一种用于测量电子设备抖动的可靠性的测量装置，包括：抖动容限估计器，用于根据从电子设备输出的输出信号，根据通过传输线输入的输入信号来估计电子设备的抖动容限 其传输长度短于预定长度，使得其不产生确定性抖动; 抖动容忍劣化量估计器，用于当通过传输线路将输入信号输入到电子设备中时，通过传输通过长传输线路来估计在输入信号中产生的确定性抖动而导致的抖动容差劣化的数量， 其传输长度大于预定长度，从而可能导致确定性抖动; 提供了一种用于估计电子设备的抖动容限的系统抖动容限估计器，以及基于抖动容限的劣化量的包括长传输线路和电子设备的系统的抖动容限。

公开(公告)号：US07263150B2

公开(公告)日：2007-08-28

申请号：US10082563

申请日：2002-02-23

申请人： Masahiro Ishida ,  Takahiro Yamaguchi ,  Mani Soma

发明人： Masahiro Ishida ,  Takahiro Yamaguchi ,  Mani Soma

IPC分类号： H04L25/38 ,  H04D3/24

CPC分类号： G01R31/31937 ,  G01R31/31725

摘要： A probability estimating apparatus and method for peak-to-peak clock skews for testing the clock skews among a plurality of clock signals distributed by a clock distributing circuit, and for estimating the generation probability of the peak-to-peak value or peak value of the clock skews. The probability estimating apparatus for peak-to-peak values in clock skews includes a clock skew estimator for estimating clock skew sequences among the plurality of clock signals under test and a probability estimator for determining a generation probability of the peak-to-peak values in the clock skews among the plurality of clock signals under test based on the clock skew sequences from the clock skew estimator by applying Rayleigh distribution. The generation probability of the peak-to-peak value is estimated based on RMS values of the clock signals and the Rayleigh distribution.

摘要翻译： 一种用于测试由时钟分配电路分配的多个时钟信号中的时钟偏差的峰 - 峰时钟偏差的概率估计装置和方法，并且用于估计峰 - 峰值或峰值的发生概率 时钟偏差。 用于时钟偏差中的峰 - 峰值的概率估计装置包括用于估计被测试的多个时钟信号之间的时钟偏移序列的时钟偏差估计器，以及用于确定在测试中的峰 - 峰值的生成概率的概率估计器 通过应用瑞利分布，基于来自时钟偏差估计器的时钟偏移序列，时钟在测试的多个时钟信号之间偏移。 基于时钟信号的RMS值和瑞利分布来估计峰峰值的发生概率。

公开(公告)号：US20070098128A1

公开(公告)日：2007-05-03

申请号：US11260665

申请日：2005-10-28

申请人： Masahiro Ishida ,  Takahiro Yamaguchi ,  Mani Soma

发明人： Masahiro Ishida ,  Takahiro Yamaguchi ,  Mani Soma

IPC分类号： H03D3/24

CPC分类号： H03K5/13 ,  G01R31/31709 ,  H03L7/0812 ,  H03L7/0891 ,  H03L7/0995 ,  H03L7/16

摘要： There is provided a clock generator for generating a single-phase clock into which jitter has been injected, having a multi-phase clock generating section for generating a plurality of clock signals having an almost equal phase difference from each other and a jitter injecting section for injecting jitter into the respective clock signals.

摘要翻译： 提供了一种时钟发生器，用于产生已经注入了抖动的单相时钟，具有用于产生彼此具有几乎相等的相位差的多个时钟信号的多相时钟产生部分，以及用于 将抖动注入相应的时钟信号。

公开(公告)号：US20060251162A1

公开(公告)日：2006-11-09

申请号：US11122262

申请日：2005-05-04

申请人： Takahiro Yamaguchi ,  Mani Soma ,  Masahiro Ishida

发明人： Takahiro Yamaguchi ,  Mani Soma ,  Masahiro Ishida

IPC分类号： H04B3/46

CPC分类号： G01R31/31709

摘要： There is provided a jitter measuring apparatus for measuring jitter in a signal-under-measurement, having a signal converting section for calculating a spectrum of the signal-under-measurement, a bandwidth calculating section for calculating frequency where a saturation rate of a value of the integrated spectrum of the signal-under-measurement becomes almost equal to a saturation rate set in advance in a band-to-be-measured set in advance as upper cutoff frequency of the band-to-be-measured to calculate the jitter and a jitter calculating section for measuring the jitter in the signal-under-measurement based on the spectaum in the band-to-be-measured of the signal-under-measurement.

摘要翻译： 提供了一种用于测量测量信号中的抖动的抖动测量装置，具有用于计算测量信号的频谱的信号转换部分，用于计算频率的饱和率的频率的带宽计算部分， 信号未测量的综合频谱几乎等于预先设定在要测量的频带中的设定​​的饱和速率，作为要测量的频带的上限截止频率以计算抖动，并且 抖动计算部分，用于根据待测信号的测量范围内的光谱测量测量信号中的抖动。

公开(公告)号：US20060184332A1

公开(公告)日：2006-08-17

申请号：US11056330

申请日：2005-02-11

申请人： Masahiro Ishida ,  Takahiro Yamaguchi ,  Mani Soma

发明人： Masahiro Ishida ,  Takahiro Yamaguchi ,  Mani Soma

IPC分类号： G01R29/26

CPC分类号： G01R31/31709 ,  G01R31/2882 ,  G01R31/31716

摘要： A testing apparatus for performing a testing on a device under test (DUT) is provided, wherein the testing apparatus includes a performance board on which the DUT is mounted; a main frame for generating a test signal for testing the DUT and determining pass/fail of the DUT on the basis of an output signal output by the DUT; a pin electronics which is provided between the main frame and the performance board and performs sending and receiving signals between the main frame and the DUT; a deterministic jitter injecting unit for receiving the output signal without passing through the pin electronics and inputting a loop signal, which is the received output signal into which a deterministic jitter is injected, to an input pin of the DUT without passing through the pin electronics; and a switching unit for determining whether the input pin of the DUT is provided with the test signal output by the pin electronics or the loop signal output by the deterministic jitter injecting unit.

摘要翻译： 提供了一种用于在被测设备（DUT）上进行测试的测试设备，其中测试设备包括安装有DUT的性能板; 用于产生用于测试DUT的测试信号和根据DUT输出的输出信号确定DUT的通过/失败的主框架; 引脚电子设备，设置在主框架和执行板之间，并在主框架和DUT之间执行发送和接收信号; 确定性抖动注入单元，用于在不通过引脚电子装置的情况下接收输出信号，并将作为确定性抖动的接收输出信号的环路信号输入到DUT的输入引脚，而不通过引脚电子器件; 以及用于确定DUT的输入引脚是否具有由引脚电子器件输出的测试信号或由确定性抖动注入单元输出的环路信号的开关单元。