公开(公告)号：US08110864B2

公开(公告)日：2012-02-07

申请号：US12327418

申请日：2008-12-03

申请人： Takashi Izumida ,  Masaki Kondo

发明人： Takashi Izumida ,  Masaki Kondo

IPC分类号： H01L29/778

CPC分类号： H01L29/7881 ,  G11C16/0483 ,  H01L21/28273 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/42324

摘要： In one aspect of the present invention, a nonvolatile semiconductor memory device may include a semiconductor substrate; a plurality of tunnel insulating films formed on the semiconductor substrate at predetermined intervals in a first direction; a plurality of floating gate electrodes each having a first portion and a second portion, the first portions being formed on the respective tunnel insulating films, the second portions being formed on the respective first portions and having smaller width than the first portions in the first direction; an inter-gate insulating film formed on the floating gate electrodes; and first and second control gate electrodes respectively formed on sidewalls, in the first direction, of the second portion of each of the plurality of floating gate electrodes with the inter-gate insulating film interposed therebetween.

摘要翻译： 在本发明的一个方面中，非易失性半导体存储器件可以包括半导体衬底; 在第一方向上以预定间隔形成在所述半导体衬底上的多个隧道绝缘膜; 多个浮置栅极，每个具有第一部分和第二部分，所述第一部分形成在相应的隧道绝缘膜上，所述第二部分形成在相应的第一部分上，并且具有比所述第一方向上的第一部分更小的宽度 ; 形成在所述浮栅电极上的栅极间绝缘膜; 以及第一和第二控制栅极电极，分别形成在多个浮置栅电极中的每一个的第二部分的第一方向的侧壁上，栅间绝缘膜插入其间。

公开(公告)号：US07986000B2

公开(公告)日：2011-07-26

申请号：US12564349

申请日：2009-09-22

申请人： Makoto Mizukami ,  Kiyohito Nishihara ,  Masaki Kondo ,  Takashi Izumida ,  Hirokazu Ishida ,  Atsushi Fukumoto ,  Fumiki Aiso ,  Daigo Ichinose ,  Tadashi Iguchi

发明人： Makoto Mizukami ,  Kiyohito Nishihara ,  Masaki Kondo ,  Takashi Izumida ,  Hirokazu Ishida ,  Atsushi Fukumoto ,  Fumiki Aiso ,  Daigo Ichinose ,  Tadashi Iguchi

IPC分类号： H01L29/76 ,  H01L21/00 ,  H01L21/84

CPC分类号： H01L27/1203 ,  H01L21/84 ,  H01L27/11521 ,  H01L27/11524

摘要： A semiconductor device is formed on a SOI substrate having a semiconductor substrate, a buried oxide film formed on the semiconductor substrate, and a semiconductor layer formed on the buried oxide film, the semiconductor substrate having a first conductive type, the semiconductor layer having a second conductive type, wherein the buried oxide film has a first opening opened therethrough for communicating the semiconductor substrate with the semiconductor layer, the semiconductor layer is arranged to have a first buried portion buried in the first opening in contact with the semiconductor substrate and a semiconductor layer main portion positioned on the first buried portion and on the buried oxide film, the semiconductor substrate has a connection layer buried in a surface of the semiconductor substrate and electrically connected to the first buried portion in the first opening, the connection layer having the second conductive type, and the semiconductor device includes a contact electrode buried in a second opening, a side surface of the contact electrode being connected to the semiconductor layer main portion, a bottom surface of the contact electrode being connected to the connection layer, the second opening passing through the semiconductor layer main portion and the buried oxide film, and the second opening reaching a surface portion of the connection layer.

摘要翻译： 半导体器件形成在具有半导体衬底的SOI衬底上，形成在半导体衬底上的掩埋氧化膜以及形成在掩埋氧化膜上的半导体层，该半导体衬底具有第一导电类型，该半导体层具有第二导电型 导电型，其中所述掩埋氧化物膜具有通过其开口的第一开口，用于使所述半导体衬底与所述半导体层连通，所述半导体层被布置为具有埋在所述第一开口中的与所述半导体衬底接触的第一掩埋部分和半导体层 主要部分位于第一掩埋部分和掩埋氧化膜上，半导体衬底具有埋在半导体衬底的表面中并与第一开口中的第一掩埋部分电连接的连接层，连接层具有第二导电 类型，并且半导体器件包括接触电极 阴极埋入第二开口中，接触电极的侧表面连接到半导体层主体部分，接触电极的底表面连接到连接层，第二开口穿过半导体层主体部分和埋设 氧化膜，第二开口到达连接层的表面部分。

公开(公告)号：US20090146203A1

公开(公告)日：2009-06-11

申请号：US12327418

申请日：2008-12-03

申请人： Takashi Izumida ,  Masaki Kondo

发明人： Takashi Izumida ,  Masaki Kondo

IPC分类号： H01L29/788

CPC分类号： H01L29/7881 ,  G11C16/0483 ,  H01L21/28273 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/42324

摘要： In one aspect of the present invention, a nonvolatile semiconductor memory device may include a semiconductor substrate; a plurality of tunnel insulating films formed on the semiconductor substrate at predetermined intervals in a first direction; a plurality of floating gate electrodes each having a first portion and a second portion, the first portions being formed on the respective tunnel insulating films, the second portions being formed on the respective first portions and having smaller width than the first portions in the first direction; an inter-gate insulating film formed on the floating gate electrodes; and first and second control gate electrodes respectively formed on sidewalls, in the first direction, of the second portion of each of the plurality of floating gate electrodes with the inter-gate insulating film interposed therebetween.

摘要翻译： 在本发明的一个方面中，非易失性半导体存储器件可以包括半导体衬底; 在第一方向上以预定间隔形成在所述半导体衬底上的多个隧道绝缘膜; 多个浮置栅极，每个具有第一部分和第二部分，所述第一部分形成在相应的隧道绝缘膜上，所述第二部分形成在相应的第一部分上，并且具有比所述第一方向上的第一部分更小的宽度 ; 形成在所述浮栅电极上的栅极间绝缘膜; 以及第一和第二控制栅极电极，分别形成在多个浮置栅电极中的每一个的第二部分的第一方向的侧壁上，栅间绝缘膜插入其间。

公开(公告)号：US20100117135A1

公开(公告)日：2010-05-13

申请号：US12564349

申请日：2009-09-22

申请人： Makoto MIZUKAMI ,  Kiyohito Nishihara ,  Masaki Kondo ,  Takashi Izumida ,  Hirokazu Ishida ,  Atsushi Fukumoto ,  Fumiki Aiso ,  Daigo Ichinose ,  Tadashi Iguchi

发明人： Makoto MIZUKAMI ,  Kiyohito Nishihara ,  Masaki Kondo ,  Takashi Izumida ,  Hirokazu Ishida ,  Atsushi Fukumoto ,  Fumiki Aiso ,  Daigo Ichinose ,  Tadashi Iguchi

IPC分类号： H01L27/12 ,  H01L21/86

CPC分类号： H01L27/1203 ,  H01L21/84 ,  H01L27/11521 ,  H01L27/11524

摘要： A semiconductor device is formed on a SOI substrate having a semiconductor substrate, a buried oxide film formed on the semiconductor substrate, and a semiconductor layer formed on the buried oxide film, the semiconductor substrate having a first conductive type, the semiconductor layer having a second conductive type, wherein the buried oxide film has a first opening opened therethrough for communicating the semiconductor substrate with the semiconductor layer, the semiconductor layer is arranged to have a first buried portion buried in the first opening in contact with the semiconductor substrate and a semiconductor layer main portion positioned on the first buried portion and on the buried oxide film, the semiconductor substrate has a connection layer buried in a surface of the semiconductor substrate and electrically connected to the first buried portion in the first opening, the connection layer having the second conductive type, and the semiconductor device includes a contact electrode buried in a second opening, a side surface of the contact electrode being connected to the semiconductor layer main portion, a bottom surface of the contact electrode being connected to the connection layer, the second opening passing through the semiconductor layer main portion and the buried oxide film, and the second opening reaching a surface portion of the connection layer.

摘要翻译： 半导体器件形成在具有半导体衬底的SOI衬底上，形成在半导体衬底上的掩埋氧化膜以及形成在掩埋氧化膜上的半导体层，该半导体衬底具有第一导电类型，该半导体层具有第二导电型 导电型，其中所述掩埋氧化物膜具有通过其开口的第一开口，用于使所述半导体衬底与所述半导体层连通，所述半导体层被布置为具有埋在所述第一开口中的与所述半导体衬底接触的第一掩埋部分和半导体层 主要部分位于第一掩埋部分和掩埋氧化膜上，半导体衬底具有埋在半导体衬底的表面中并与第一开口中的第一掩埋部分电连接的连接层，连接层具有第二导电 类型，并且半导体器件包括接触电极 阴极埋入第二开口中，接触电极的侧表面连接到半导体层主体部分，接触电极的底表面连接到连接层，第二开口穿过半导体层主体部分和埋设 氧化膜，第二开口到达连接层的表面部分。

公开(公告)号：US20080179659A1

公开(公告)日：2008-07-31

申请号：US12021003

申请日：2008-01-28

申请人： Toshiyuki Enda ,  Hiroyoshi Tanimoto ,  Takashi Izumida

发明人： Toshiyuki Enda ,  Hiroyoshi Tanimoto ,  Takashi Izumida

IPC分类号： H01L27/115

CPC分类号： H01L27/115 ,  H01L27/11568 ,  H01L27/11578 ,  H01L27/11582 ,  H01L29/792 ,  H01L29/7926

摘要： A nonvolatile semiconductor memory device relating to one embodiment of this invention includes a substrate, a plurality of memory strings formed on said substrate, said memory string having a first select gate transistor, a plurality of memory cells and a second select gate transistor, said first select gate transistor having a first pillar semiconductor, a first gate insulation layer formed around said first pillar semiconductor and a first gate electrode being formed around said first gate insulation layer; said memory cell having a second pillar semiconductor, a first insulation layer formed around said second pillar semiconductor, a storage layer formed around said first insulation layer, a second insulation layer formed around said storage layer and first to nth electrodes (n is a natural number 2 or more) being formed around said second insulation layer, said first to nth electrodes being spread in two dimensions respectively, said second select gate transistor having a third pillar semiconductor, a second gate insulation layer formed around said third pillar semiconductor and a second gate electrode being formed around said second gate insulation layer, and a channel region of at least either said first select gate transistor or said second select gate transistor formed by an opposite conductive type semiconductor to a source region and a drain region.

摘要翻译： 关于本发明的一个实施例的非易失性半导体存储器件包括衬底，形成在所述衬底上的多个存储器串，所述存储器串具有第一选择栅晶体管，多个存储单元和第二选择栅晶体管，所述第一 选择具有第一柱状半导体的栅极晶体管，形成在所述第一柱状半导体周围的第一栅极绝缘层和围绕所述第一栅极绝缘层形成的第一栅极电极; 所述存储单元具有第二柱状半导体，围绕所述第二柱状半导体形成的第一绝缘层，围绕所述第一绝缘层形成的存储层，形成在所述存储层和第一至第n电极周围的第二绝缘层（n为自然数） 2个或更多个），所述第一至第n电极分别以两维扩展，所述第二选择栅晶体管具有第三柱半导体，围绕所述第三柱半导体形成的第二栅绝缘层和第二栅极 形成在所述第二栅极绝缘层周围的电极，以及至少所述第一选择栅极晶体管或所述第二选择栅极晶体管的沟道区域，所述沟道区域由相对的导电型半导体形成为源极区域和漏极区域。

公开(公告)号：US20070210355A1

公开(公告)日：2007-09-13

申请号：US11713803

申请日：2007-03-05

申请人： Takashi Izumida

发明人： Takashi Izumida

IPC分类号： H01L29/76

CPC分类号： H01L29/785 ,  H01L29/6659 ,  H01L29/7843

摘要： A semiconductor device includes: an insulating layer; a semiconductor fin protruding from the insulating layer, extending in a first direction parallel to a major surface of the insulating layer, and having a source region, a channel section, and a drain region arranged in the first direction; a gate electrode opposed at least to a side face of the channel section in the semiconductor fin and extending in a second direction that is substantially orthogonal to the first direction and parallel to the major surface of the insulating layer; an insulating film interposed between the semiconductor fin and the gate electrode; a spacer layer provided on the channel section; a sidewall insulating layer provided adjacent to a side face of the spacer layer substantially parallel to the second direction; and a stress liner. The stress liner covers the sidewall insulating layer and the spacer layer and has an intrinsic stress for distorting the semiconductor fin. The sidewall insulating layer has a thickness of 45 nanometers (nm) or more in the first direction, and the spacer layer has a height of 105 nanometers (nm) or more.

摘要翻译： 半导体器件包括：绝缘层; 从所述绝缘层突出的半导体鳍片，沿着与所述绝缘层的主表面平行的第一方向延伸，并且具有沿所述第一方向排列的源极区域，沟道部分和漏极区域; 至少与所述半导体鳍片中的沟道部分的侧面相对且在与所述第一方向大致正交且平行于所述绝缘层的主表面的第二方向上延伸的栅电极; 介于所述半导体鳍片和所述栅电极之间的绝缘膜; 间隔层，设置在通道部分上; 侧壁绝缘层，设置成与所述间隔层的与所述第二方向大致平行的侧面相邻; 和应力衬垫。 应力衬垫覆盖侧壁绝缘层和间隔层，并且具有使半导体翅片变形的固有应力。 侧壁绝缘层在第一方向上具有45纳米（nm）以上的厚度，间隔层的高度为105纳米（nm）以上。

公开(公告)号：US20070170509A1

公开(公告)日：2007-07-26

申请号：US11401928

申请日：2006-04-12

申请人： Takashi Izumida

发明人： Takashi Izumida

IPC分类号： H01L27/12

CPC分类号： H01L29/785 ,  H01L29/66818 ,  H01L29/7851

摘要： A semiconductor device includes a Fin, a source region and a drain region, a first extension region, a second extension region and a channel region. The Fin is formed on a major surface of a semiconductor substrate. The source region and drain region are formed at both end portions of the Fin. The first extension region is formed between the source region and the drain region within the Fin in contact with the source region. The second extension region is formed between the source region and the drain region within the Fin in contact with the drain region. The channel region is located between the first extension region and the second extension region within the Fin, a height of the Fin of the channel region being greater than a height of the Fin of each of the first extension region and the second extension region.

摘要翻译： 半导体器件包括Fin，源极区和漏极区，第一延伸区，第二延伸区和沟道区。 鳍形成在半导体衬底的主表面上。 源极区域和漏极区域形成在鳍片的两个端部处。 第一延伸区形成在与源极区域接触的鳍内的源极区域和漏极区域之间。 第二延伸区域形成在与漏极区域接触的鳍内的源极区域和漏极区域之间。 沟道区域位于鳍内的第一延伸区域和第二延伸区域之间，沟道区域的鳍的高度大于第一延伸区域和第二延伸区域中的每一个的鳍的高度。

公开(公告)号：US07115476B1

公开(公告)日：2006-10-03

申请号：US11201264

申请日：2005-08-11

申请人： Takashi Izumida

发明人： Takashi Izumida

IPC分类号： H01L21/336

CPC分类号： H01L29/78642 ,  H01L21/28273 ,  H01L27/0207 ,  H01L27/115 ,  H01L27/11519 ,  H01L27/11551 ,  H01L27/11556 ,  H01L29/66772 ,  H01L29/66825 ,  H01L29/7881

摘要： A method of manufacturing a semiconductor device includes forming a mask layer on a semiconductor substrate, etching the semiconductor substrate using the mask layer as a mask, thereby forming a semiconductor pillar, doping an impurity into the semiconductor substrate, thereby forming a first source/drain region in part of the semiconductor substrate, which is located under the semiconductor pillar, forming a gate insulating film on the semiconductor substrate, which contacts a side surface of the semiconductor pillar, forming a gate electrode on a side surface of the gate insulating film, forming a first insulating layer on the gate electrode, which contacts a side surface of the semiconductor pillar, and doping the impurity into the first insulating layer, thereby forming a second source/drain region in part of the semiconductor pillar, which is located on a side surface of the first insulating layer.

摘要翻译： 半导体器件的制造方法包括在半导体衬底上形成掩模层，使用掩模层作为掩模蚀刻半导体衬底，从而形成半导体柱，将杂质掺杂到半导体衬底中，从而形成第一源极/漏极 位于所述半导体柱下方的半导体衬底的一部分中，在所述半导体衬底上形成与所述半导体柱的侧面接触的栅极绝缘膜，在所述栅极绝缘膜的侧面形成栅电极， 在所述栅电极上形成第一绝缘层，所述第一绝缘层与所述半导体柱的侧表面接触，并将所述杂质掺杂到所述第一绝缘层中，从而在半导体柱的一部分中形成第二源/漏区， 第一绝缘层的侧表面。

公开(公告)号：US08987829B2

公开(公告)日：2015-03-24

申请号：US12100621

申请日：2008-04-10

申请人： Yoshiaki Shimooka ,  Takashi Izumida ,  Hiroki Okamoto

发明人： Yoshiaki Shimooka ,  Takashi Izumida ,  Hiroki Okamoto

IPC分类号： H01L27/092 ,  H01L21/8238 ,  H01L29/78

CPC分类号： H01L21/823807 ,  H01L27/092 ,  H01L29/7843 ,  H01L29/7846

摘要： A semiconductor device may include a p-channel semiconductor active region and an n-channel semiconductor active region. An element isolation insulating layer electrically isolates the p-channel semiconductor active region from the n-channel semiconductor active region. An insulating layer made of a different material, being in contact with both ends, in its channel length direction, of the p-channel semiconductor active region applies a compression stress in the channel length direction to a channel of the p-channel semiconductor active region. The p-channel semiconductor active region is surrounded by the insulating layer, in the channel length direction, of the p-channel semiconductor active region and by the element isolation insulating layer, parallel to the channel length direction, of the p-channel semiconductor active region. The n-channel semiconductor active region is surrounded by the element isolation insulating layer.

摘要翻译： 半导体器件可以包括p沟道半导体有源区和n沟道半导体有源区。 元件隔离绝缘层将p沟道半导体有源区与n沟道半导体有源区电隔离。 由p沟道半导体有源区的沿其沟道长度方向与两端接触的不同材料制成的绝缘层将沟道长度方向的压缩应力施加到p沟道半导体有源区的沟道 。 p沟道半导体有源区被p沟道半导体有源区的沟道长度方向的绝缘层和与沟道长度方向平行的元件隔离绝缘层包围， 地区。 n沟道半导体有源区被元件隔离绝缘层包围。

公开(公告)号：US20110024824A1

公开(公告)日：2011-02-03

申请号：US12820351

申请日：2010-06-22

申请人： Yasuhiro SHIMURA ,  Takashi Izumida ,  Mutsuo Morikado ,  Kiyomi Naruke

发明人： Yasuhiro SHIMURA ,  Takashi Izumida ,  Mutsuo Morikado ,  Kiyomi Naruke

IPC分类号： H01L29/792 ,  H01L21/28

CPC分类号： H01L29/42324 ,  H01L27/11521 ,  H01L29/40114 ,  H01L29/66825 ,  H01L29/7881

摘要： According to one embodiment, a nonvolatile semiconductor memory device includes a semiconductor layer and a transistor. The transistor includes: a source region, a drain region, and a channel region provided in the semiconductor layer, the channel region being between the source and drain regions; a gate insulating film provided on the channel region; a charge layer provided on the gate insulating film, the charge layer having a side portion and a apical portion;an inter-electrode insulating film covering the side portion and the apical portion; and a control gate provided on the inter-electrode insulating film. The control gate includes: a side-portion conductive layer opposing the side portion; and an apical-portion conductive layer opposing the apical portion.The apical-portion conductive layer has a work function higher than a work function of the charge layer and higher than a work function of the side-portion conductive layer.

摘要翻译： 根据一个实施例，非易失性半导体存储器件包括半导体层和晶体管。 晶体管包括：源极区，漏极区和设置在半导体层中的沟道区，沟道区位于源区和漏区之间; 设置在沟道区上的栅极绝缘膜; 设置在所述栅极绝缘膜上的电荷层，所述电荷层具有侧部和顶部; 覆盖所述侧部和所述顶部的电极间绝缘膜; 以及设置在电极间绝缘膜上的控制栅极。 控制门包括：与侧部相对的侧部导电层; 以及与顶端部分相对的顶端部导电层。 顶部导电层的功函数高于电荷层的功函数，高于侧面导电层的功函数。