公开(公告)号：US06388864B1

公开(公告)日：2002-05-14

申请号：US09651410

申请日：2000-08-30

申请人： Takuji Nakagawa ,  Yoshikazu Takagi ,  Yasunobu Yoneda

发明人： Takuji Nakagawa ,  Yoshikazu Takagi ,  Yasunobu Yoneda

IPC分类号： H01G4228

CPC分类号： H01G4/232 ,  H01G2/14

摘要： A ceramic electronic component includes a ceramic electronic component body having two end faces opposing each other, side faces connecting the two end faces, and terminal electrodes formed on each end face; and terminal members, each including a metal being soldered to one of the terminal electrodes. Each of the terminal electrodes includes a metal layer formed only on the end face, a conductive resin layer formed on the metal layer, the conductive resin layer including metal powder and resin, and a plating film on the conductive resin layer.

摘要翻译： 陶瓷电子部件包括陶瓷电子部件体，该陶瓷电子部件主体具有彼此相对的两个端面，连接两个端面的侧面和形成在各个端面上的端子电极; 以及端子构件，每个端子构件包括被焊接到一个端子电极的金属。 每个端子电极包括仅在端面形成的金属层，形成在金属层上的导电树脂层，包括金属粉末和树脂的导电树脂层和在导电树脂层上的镀膜。

公开(公告)号：US06331932B1

公开(公告)日：2001-12-18

申请号：US09482225

申请日：2000-01-13

申请人： Fumiyuki Kobayashi ,  Kazuaki Kawabata ,  Yasushi Ueno ,  Yasunobu Yoneda

发明人： Fumiyuki Kobayashi ,  Kazuaki Kawabata ,  Yasushi Ueno ,  Yasunobu Yoneda

IPC分类号： H01G406

CPC分类号： H01G4/1227

摘要： A monolithic ceramic capacitor includes a sintered ceramic compact having a core-shell structure, a plurality of internal electrodes arranged in and separated by the ceramic sintered compact so as to overlap in the thickness direction, and a plurality of external electrodes formed on the outermost faces of the ceramic sintered compact. In the core-shell structure, cores are composed of a particulate dielectric ceramic, and shells are formed on the cores and are composed of a material having a dielectric constant lower than that of the dielectric ceramic. The area ratio of the cores to the shells lies in a range of 7:3 to 3:7 in a cross-section of the sintered ceramic compact in an arbitrary direction. The core-shell structure can achieve further miniaturization and higher capacitance of the monolithic ceramic capacitor, in addition to superior temperature characteristics.

摘要翻译： 一种叠层陶瓷电容器包括具有核 - 壳结构的烧结陶瓷压块，布置在陶瓷烧结体中并沿着厚度方向重叠的多个内部电极和形成在最外面的多个外部电极 的陶瓷烧结体。 在核 - 壳结构中，芯由颗粒介电陶瓷组成，并且壳形成在芯上，并且由介电常数低于电介质陶瓷的材料构成。 在烧结陶瓷压块的任意方向的横截面中，芯与壳的面积比在7:3〜3:7的范围内。 核壳结构除了具有优异的温度特性之外，还可以实现单片陶瓷电容器的进一步的小型化和更高的电容。

公开(公告)号：US06292354B1

公开(公告)日：2001-09-18

申请号：US09603043

申请日：2000-06-26

申请人： Fumiyuki Kobayashi ,  Kazuaki Kawabata ,  Yasushi Ueno ,  Yoshikazu Takagi ,  Yasunobu Yoneda

发明人： Fumiyuki Kobayashi ,  Kazuaki Kawabata ,  Yasushi Ueno ,  Yoshikazu Takagi ,  Yasunobu Yoneda

IPC分类号： H01G406

CPC分类号： H01G4/1227 ,  C04B35/4682

摘要： The present invention provides a laminated ceramic capacitor having good temperature characteristics, and suitable for attaining miniaturization, large capacitance and low production cost besides having high reliability in the high temperature load test, wherein a plurality of inner electrodes are formed in a ceramic sintered body comprising a reduction resistant dielectric ceramic in which grains having a core-shell structure and grains having a homogeneous structure are mixed together, and wherein outer electrodes are formed on the outer surfaces of the ceramic sintered body, the area ratio between the total area of the grains having the core-shell structure and the total area of the grains having the homogeneous structure being adjusted within a the range of about 2:8 to 4:6 when a cross section is observed along an arbitrary direction of the ceramic sintered body.

摘要翻译： 本发明提供一种具有良好温度特性的层压陶瓷电容器，除了在高温负载试验中具有高可靠性之外，还适合于实现小型化，大电容化和低生产成本，其中在陶瓷烧结体中形成多个内电极，其包括 将具有核 - 壳结构的晶粒和具有均匀结构的晶粒混合在一起的抗还原电介质陶瓷，其中在陶瓷烧结体的外表面上形成外电极，晶粒的总面积之间的面积比 当沿着陶瓷烧结体的任意方向观察截面时，具有核 - 壳结构和具有均匀结构的晶粒的总面积在约2：8〜4：6的范围内调整。

公开(公告)号：US5430429A

公开(公告)日：1995-07-04

申请号：US127747

申请日：1993-09-27

申请人： Kazutaka Nakamura ,  Hiroyuki Kubota ,  Yasunobu Yoneda ,  Akinori Nakayama ,  Tohru Tominaga ,  Tomoaki Ushiro

发明人： Kazutaka Nakamura ,  Hiroyuki Kubota ,  Yasunobu Yoneda ,  Akinori Nakayama ,  Tohru Tominaga ,  Tomoaki Ushiro

IPC分类号： H01C1/02

CPC分类号： H01C1/02

摘要： A resistor 1 in which at least one resistance film 4 is embedded in a ceramic sintered body 3, glass is diffused into the sintered body 3 to form a glass diffusion layer 6, and both end faces 4a and 4b of the resistance film 4 are respectively exposed to both end faces 3a and 3b of the ceramic sintered body 3.

摘要翻译： 在陶瓷烧结体3中嵌入有至少一个电阻膜4的电阻器1，将玻璃扩散到烧结体3中，形成玻璃扩散层6，电阻膜4的两端面4a，4b分别 暴露于陶瓷烧结体3的两个端面3a和3b。

公开(公告)号：US5324986A

公开(公告)日：1994-06-28

申请号：US901750

申请日：1992-06-22

申请人： Yasushi Ueno ,  Akinori Nakayama ,  Kazutaka Nakamura ,  Yasunobu Yoneda ,  Yukio Sakabe ,  Tomoaki Ushiro

发明人： Yasushi Ueno ,  Akinori Nakayama ,  Kazutaka Nakamura ,  Yasunobu Yoneda ,  Yukio Sakabe ,  Tomoaki Ushiro

IPC分类号： H01C7/10 ,  H01C7/112 ,  H01L23/053 ,  H01L23/14 ,  H01L23/15

CPC分类号： H01C7/10 ,  H01C7/112

摘要： A chip type varistor in which first and second inner electrodes are embedded in a sintered body obtained by laminating a plurality of semiconductor ceramics layers so as not to be overlapped with each other in the direction of thickness of the ceramics layers, respective one edges of the first and second inner electrodes are led out to one and the other of a pair of side surfaces opposed to each other of the sintered body and are electrically connected to outer electrodes formed on the pair of side surfaces of the sintered body, respectively, a non-connected type inner electrode which is not electrically connected to the above described outer electrodes is embedded in the sintered body, and the non-connected type inner electrode is arranged so as to be overlapped with the first and second inner electrodes while being separated by the semiconductor ceramics layer.

摘要翻译： 一种芯片型变阻器，其中第一和第二内部电极嵌入在通过层叠多个半导体陶瓷层而不是在陶瓷层的厚度方向上彼此不重叠而获得的烧结体中， 第一和第二内部电极被引出到烧结体彼此相对的一对侧表面中的一个和另一个，并且分别与形成在烧结体的一对侧表面上的外部电极电连接， 不与上述外部电极电连接的连接型内部电极嵌入在烧结体中，非连接型内部电极配置成与第一和第二内部电极重叠，同时被 半导体陶瓷层。

公开(公告)号：US5119062A

公开(公告)日：1992-06-02

申请号：US615369

申请日：1990-11-19

申请人： Kazutaka Nakamura ,  Hiroaki Taira ,  Tohru Higashi ,  Akinori Nakayama ,  Yasunobu Yoneda ,  Yukio Sakabe

发明人： Kazutaka Nakamura ,  Hiroaki Taira ,  Tohru Higashi ,  Akinori Nakayama ,  Yasunobu Yoneda ,  Yukio Sakabe

IPC分类号： H01C7/10

CPC分类号： H01C7/10

摘要： A monolithic type varistor in which a plurality of inner electrodes are arranged in a sintered body composed of semiconductor ceramics so as to be overlapped with each other while being separated by semiconductor ceramic layers. The plurality of inner electrodes are electrically connected to first and second outer electrodes formed on both end surfaces of the sintered body. One or more non-connected type inner electrodes are arranged between adjacent ones of the plurality of inner electrodes and are not electrically connected to the outer electrodes, each of the non-connected type inner electrodes being spaced apart from each adjacent inner electrode or non-connected type inner electrode while being separated therefrom by a semiconductor ceramic layer. Voltage non-linearity is obtained by Schottky barriers formed at the interface of the inner electrode and the semiconductor ceramic layer and the interface of the non-connected type inner electrode and the semiconductor ceramic layer. The value of the number of grain boundaries between semiconductor particles in at least one semiconductor ceramic layer is two or less.

摘要翻译： 一种单片型压敏电阻，其中多个内部电极被布置在由半导体陶瓷组成的烧结体中，以便在被半导体陶瓷层分离的同时彼此重叠。 多个内部电极电连接到形成在烧结体的两个端面上的第一和第二外部电极。 一个或多个非连接型内部电极布置在多个内部电极的相邻的内部电极之间，并且不与外部电极电连接，每个非连接型内部电极与每个相邻的内部电极或非电连接的内部电极间隔开， 连接型内部电极，同时由半导体陶瓷层分离。 通过在内部电极和半导体陶瓷层的界面处形成的肖特基势垒以及非连接型内部电极和半导体陶瓷层的界面获得电压非线性。 至少一个半导体陶瓷层中的半导体粒子之间的晶界数的值为2以下。

公开(公告)号：US5075665A

公开(公告)日：1991-12-24

申请号：US404838

申请日：1989-09-08

申请人： Hiroaki Taira ,  Kazutaka Nakamura ,  Yasunobu Yoneda ,  Yukio Sakabe ,  Yutaka Shimahara

发明人： Hiroaki Taira ,  Kazutaka Nakamura ,  Yasunobu Yoneda ,  Yukio Sakabe ,  Yutaka Shimahara

IPC分类号： H01C1/14 ,  H01C7/102

CPC分类号： H01C7/102 ,  H01C1/14

摘要： Respective first end portions of first and second internal electrodes are exposed at respective end surfaces of a varistor body, which is in the form of a rectangular parallelepiped. These end surfaces of the varistor body are covered with low resistance parts which include ceramic material in order to prevent the internal electrodes from decomposition. External electrodes are formed on the low resistance parts, so as, to be electrically connected with corresponding ones of the internal electrodes through the low resistance parts.

摘要翻译： 第一和第二内部电极的相应的第一端部暴露在可变形电阻体的相应的端面上，该非线性电阻体是矩形平行六面体的形式。 可变电阻体的这些端面由包括陶瓷材料的低电阻部分覆盖，以防止内部电极分解。 外部电极形成在低电阻部分上，以便通过低电阻部分与相应的内部电极电连接。

公开(公告)号：US4535064A

公开(公告)日：1985-08-13

申请号：US613628

申请日：1984-05-24

申请人： Yasunobu Yoneda

发明人： Yasunobu Yoneda

IPC分类号： C04B35/468 ,  H01G4/12 ,  C04B35/46

CPC分类号： H01G4/1272 ,  C04B35/4682

摘要： Ceramic compositions having (1) a mixture comprised of barium titanate, zirconium oxide and one or more of cerium oxide, neodymium oxide, lanthanum oxide and an oxide of at least one of lanthanides having atomic numbers 59 to 66 in specific ratios and (2) 0.01 to 0.4% by weight (calculated as Mn based on the weight of the mixture) manganese oxide. Such compositions form reduction-reoxidation type semiconducting capacitors of reduced size and increased capacitance per unit area.

摘要翻译： 陶瓷组合物，其具有（1）钛酸钡，氧化锆和一种或多种氧化铈，氧化钕，氧化镧和至少一种具有比例的原子序数为59至66的镧系元素的氧化物的混合物，（2） 0.01〜0.4重量％（以混合物重量计的Mn计算）氧化锰。 这种组合物形成减小 - 再氧化型半导体电容器，其尺寸减小并且每单位面积增加电容。