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    Laminated varistor
    1.
    发明授权
    Laminated varistor 失效
    层压变阻器

    公开(公告)号：US5075665A

    公开(公告)日：1991-12-24

    申请号：US404838

    申请日：1989-09-08

    申请人： Hiroaki Taira ,  Kazutaka Nakamura ,  Yasunobu Yoneda ,  Yukio Sakabe ,  Yutaka Shimahara

    发明人： Hiroaki Taira ,  Kazutaka Nakamura ,  Yasunobu Yoneda ,  Yukio Sakabe ,  Yutaka Shimahara

    IPC分类号： H01C1/14 ,  H01C7/102

    CPC分类号： H01C7/102 ,  H01C1/14

    摘要： Respective first end portions of first and second internal electrodes are exposed at respective end surfaces of a varistor body, which is in the form of a rectangular parallelepiped. These end surfaces of the varistor body are covered with low resistance parts which include ceramic material in order to prevent the internal electrodes from decomposition. External electrodes are formed on the low resistance parts, so as, to be electrically connected with corresponding ones of the internal electrodes through the low resistance parts.

    摘要翻译： 第一和第二内部电极的相应的第一端部暴露在可变形电阻体的相应的端面上，该非线性电阻体是矩形平行六面体的形式。 可变电阻体的这些端面由包括陶瓷材料的低电阻部分覆盖，以防止内部电极分解。 外部电极形成在低电阻部分上，以便通过低电阻部分与相应的内部电极电连接。

    Monolithic type varistor
    2.
    发明授权
    Monolithic type varistor 失效
    单片类型变量

    公开(公告)号：US5119062A

    公开(公告)日：1992-06-02

    申请号：US615369

    申请日：1990-11-19

    申请人： Kazutaka Nakamura ,  Hiroaki Taira ,  Tohru Higashi ,  Akinori Nakayama ,  Yasunobu Yoneda ,  Yukio Sakabe

    发明人： Kazutaka Nakamura ,  Hiroaki Taira ,  Tohru Higashi ,  Akinori Nakayama ,  Yasunobu Yoneda ,  Yukio Sakabe

    IPC分类号： H01C7/10

    CPC分类号： H01C7/10

    摘要： A monolithic type varistor in which a plurality of inner electrodes are arranged in a sintered body composed of semiconductor ceramics so as to be overlapped with each other while being separated by semiconductor ceramic layers. The plurality of inner electrodes are electrically connected to first and second outer electrodes formed on both end surfaces of the sintered body. One or more non-connected type inner electrodes are arranged between adjacent ones of the plurality of inner electrodes and are not electrically connected to the outer electrodes, each of the non-connected type inner electrodes being spaced apart from each adjacent inner electrode or non-connected type inner electrode while being separated therefrom by a semiconductor ceramic layer. Voltage non-linearity is obtained by Schottky barriers formed at the interface of the inner electrode and the semiconductor ceramic layer and the interface of the non-connected type inner electrode and the semiconductor ceramic layer. The value of the number of grain boundaries between semiconductor particles in at least one semiconductor ceramic layer is two or less.

    摘要翻译： 一种单片型压敏电阻，其中多个内部电极被布置在由半导体陶瓷组成的烧结体中，以便在被半导体陶瓷层分离的同时彼此重叠。 多个内部电极电连接到形成在烧结体的两个端面上的第一和第二外部电极。 一个或多个非连接型内部电极布置在多个内部电极的相邻的内部电极之间，并且不与外部电极电连接，每个非连接型内部电极与每个相邻的内部电极或非电连接的内部电极间隔开， 连接型内部电极，同时由半导体陶瓷层分离。 通过在内部电极和半导体陶瓷层的界面处形成的肖特基势垒以及非连接型内部电极和半导体陶瓷层的界面获得电压非线性。 至少一个半导体陶瓷层中的半导体粒子之间的晶界数的值为2以下。

    Chip type varistor
    3.
    发明授权
    Chip type varistor 失效
    片式压敏电阻

    公开(公告)号：US5324986A

    公开(公告)日：1994-06-28

    申请号：US901750

    申请日：1992-06-22

    申请人： Yasushi Ueno ,  Akinori Nakayama ,  Kazutaka Nakamura ,  Yasunobu Yoneda ,  Yukio Sakabe ,  Tomoaki Ushiro

    发明人： Yasushi Ueno ,  Akinori Nakayama ,  Kazutaka Nakamura ,  Yasunobu Yoneda ,  Yukio Sakabe ,  Tomoaki Ushiro

    IPC分类号： H01C7/10 ,  H01C7/112 ,  H01L23/053 ,  H01L23/14 ,  H01L23/15

    CPC分类号： H01C7/10 ,  H01C7/112

    摘要： A chip type varistor in which first and second inner electrodes are embedded in a sintered body obtained by laminating a plurality of semiconductor ceramics layers so as not to be overlapped with each other in the direction of thickness of the ceramics layers, respective one edges of the first and second inner electrodes are led out to one and the other of a pair of side surfaces opposed to each other of the sintered body and are electrically connected to outer electrodes formed on the pair of side surfaces of the sintered body, respectively, a non-connected type inner electrode which is not electrically connected to the above described outer electrodes is embedded in the sintered body, and the non-connected type inner electrode is arranged so as to be overlapped with the first and second inner electrodes while being separated by the semiconductor ceramics layer.

    摘要翻译： 一种芯片型变阻器，其中第一和第二内部电极嵌入在通过层叠多个半导体陶瓷层而不是在陶瓷层的厚度方向上彼此不重叠而获得的烧结体中， 第一和第二内部电极被引出到烧结体彼此相对的一对侧表面中的一个和另一个，并且分别与形成在烧结体的一对侧表面上的外部电极电连接， 不与上述外部电极电连接的连接型内部电极嵌入在烧结体中，非连接型内部电极配置成与第一和第二内部电极重叠，同时被 半导体陶瓷层。

    Noise filter having non-linear voltage-dependent resistor body with a resistive layer
    4.
    发明授权
    Noise filter having non-linear voltage-dependent resistor body with a resistive layer 失效
    噪声滤波器具有带电阻层的非线性电压相关电阻体

    公开(公告)号：US5412357A

    公开(公告)日：1995-05-02

    申请号：US036438

    申请日：1993-03-24

    申请人： Kazutaka Nakamura ,  Hiroji Tani ,  Yasunobu Yoneda ,  Yukio Sakabe

    发明人： Kazutaka Nakamura ,  Hiroji Tani ,  Yasunobu Yoneda ,  Yukio Sakabe

    IPC分类号： H01C7/10 ,  H01G4/40 ,  H03H1/02 ,  H03H7/01 ,  H03H7/06

    CPC分类号： H03H1/02 ,  H03H2001/0085

    摘要： A noise filter including semi-conductor ceramics having voltage non-linearity characteristics. End surface electrodes are formed on a pair of opposing end surfaces of the semi-conductor ceramics and side surface electrodes are formed on a pair of side surfaces thereof. A first inner electrode is formed inside the semi-conductor ceramics having one end surface electrically connected to one of the end surface electrodes. A second inner electrode is formed inside the semi-conductor ceramics so as to be overlapped with the first inner electrode and separated therefrom by a ceramic layer. Both end surfaces of the second inner electrode are electrically connected to the pair of side surface electrodes. At least one resistance layer is embedded in the semi-conductor ceramics so that both end surfaces of the resistance layer are electrically connected to the pair of end surface electrodes.

    摘要翻译： 一种噪声滤波器，包括具有电压非线性特性的半导体陶瓷。 端面电极形成在半导体陶瓷的一对相对端面上，侧面电极形成在其一对侧面上。 第一内部电极形成在半导体陶瓷的内部，其一端表面电连接到一个端面电极。 第二内部电极形成在半导体陶瓷的内部，以与第一内部电极重叠并与陶瓷层分离。 第二内部电极的两端面与一对侧面电极电连接。 在半导体陶瓷中嵌入至少一个电阻层，使得电阻层的两个端面与一对端面电极电连接。

    Thermistor and method of producing the same
    7.
    发明授权
    Thermistor and method of producing the same 失效
    热敏电阻及其制造方法

    公开(公告)号：US4912450A

    公开(公告)日：1990-03-27

    申请号：US237033

    申请日：1988-08-25

    申请人： Yasunobu Yoneda ,  Michihiro Murata ,  Harufumi Mandai ,  Yukio Sakabe ,  Yukio Banba

    发明人： Yasunobu Yoneda ,  Michihiro Murata ,  Harufumi Mandai ,  Yukio Sakabe ,  Yukio Banba

    IPC分类号： H01C7/04

    CPC分类号： H01C7/04 ,  Y10T29/49092

    摘要： A method for producing negative temperature coefficient thermistor units, comprising the steps of forming a pair of green sheets of insulating ceramic material, stacking the green sheets interposing therebetween in predetermined areas a layer of paste for thermistor elements; providing for each thermistor unit a coating of paste to be formed into internal electrodes; cutting the stacked sheets into individual thermistor units; co-firing the thermistor units whereby the thermistor element is enclosed in an envelope of sintered ceramic material or sandwiched between two layers of sintered ceramic material. A pair of external electrodes is then provided on each thermistor unit.

    摘要翻译： 一种制造负温度系数热敏电阻单元的方法，包括以下步骤：形成一对绝缘陶瓷材料，将预定区域之间的生片层叠在一起，形成热敏电阻元件用糊料; 为每个热敏电阻单元提供待形成内部电极的糊状涂层; 将堆叠的片材切割成单独的热敏电阻单元; 共烧烧热敏电阻单元，由此将热敏电阻元件封装在烧结陶瓷材料的外壳中或夹在两层烧结陶瓷材料之间。 然后在每个热敏电阻单元上提供一对外部电极。

    Method of manufacturing electronic part, electronic part and electroless plating method
    9.
    发明授权
    Method of manufacturing electronic part, electronic part and electroless plating method 有权
    电子零件，电子零件和化学镀方法的制造方法

    公开(公告)号：US06780456B2

    公开(公告)日：2004-08-24

    申请号：US10315949

    申请日：2002-12-11

    申请人： Tatsuo Kunishi ,  Toshi Numata ,  Junichi Saitoh ,  Yukio Sakabe

    发明人： Tatsuo Kunishi ,  Toshi Numata ,  Junichi Saitoh ,  Yukio Sakabe

    IPC分类号： B05D512

    CPC分类号： H05K3/244 ,  C23C18/1607 ,  C23C18/1651 ,  C23C18/1669 ,  C23C18/34 ,  C23C18/36 ,  C23C18/44 ,  C23C18/54

    摘要： A work piece is mixed with Ni pieces having an average diameter of 1 mm and exhibiting catalytic activity to oxidation reaction of sodium phosphinate (NaH2PO2) added as a reducing agent in a plating bath containing the reducing agent and a Ni salt to form a Ni—P film on an electrode made of Cu, Ag or Ag—Pd by auto-catalytic electroless plating. Then, the work piece is dipped in a plating bath containing an Au salt to form an Au film on the surface of the Ni—P film by substitutional electroless plating. This method is capable of forming a desired plating film only on a desired portion at a low cost.

    摘要翻译： 将工件与平均直径为1mm的Ni片混合，并且在含有还原剂的镀浴和Ni盐中显示出对作为还原剂加入的次膦酸钠（NaH 2 PO 2）的氧化反应的催化活性，形成Ni- 通过自动催化无电镀法在Cu，Ag或Ag-Pd制成的电极上的P膜。 然后，将工件浸入含有Au盐的镀浴中，通过替代无电镀在Ni-P膜的表面上形成Au膜。 该方法能够以低成本仅在期望的部分形成期望的镀膜。

    Barium titanate semiconductive ceramic
    10.
    发明授权
    Barium titanate semiconductive ceramic 有权
    钛酸钡半导体陶瓷

    公开(公告)号：US06472339B2

    公开(公告)日：2002-10-29

    申请号：US09157062

    申请日：1998-09-18

    申请人： Mitsutoshi Kawamoto ,  Hideaki Niimi ,  Ryouichi Urahara ,  Yukio Sakabe

    发明人： Mitsutoshi Kawamoto ,  Hideaki Niimi ,  Ryouichi Urahara ,  Yukio Sakabe

    IPC分类号： C04B35468

    CPC分类号： B82Y30/00 ,  C01G23/006 ,  C01P2002/50 ,  C01P2002/76 ,  C01P2002/77 ,  C01P2004/62 ,  C01P2004/64 ,  C04B35/4682

    摘要： The present invention provides barium titanate semiconductive ceramic having low specific resistance at room temperature and high withstand voltage, which fully satisfies the demand for enhancing withstand voltage. The average ceramic grain size of the barium titanate semiconductive ceramic is controlled to about 0.9 &mgr;m or less. By this control, the ceramic possesses low specific resistance at room temperature and high withstand voltage fully satisfying a recent demand for enhancing withstand voltage and may suitably used for applications such as controlling temperature and limiting current, or in exothermic devices for constant temperature. Accordingly, the barium titanate semiconductive ceramic enables an apparatus using the same to have enhanced performance and reduced size.

    摘要翻译： 本发明提供了在室温下具有低电阻率和高耐压的钛酸钡半导体陶瓷，其完全满足提高耐电压的要求。 钛酸钡半导体陶瓷的平均陶瓷粒径控制在0.9μm以下。 通过该控制，陶瓷在室温下具有低的电阻率和高耐受电压，完全满足了近来对提高耐受电压的要求，并且可以适用于诸如控制温度和限制电流的应用，或用于恒温的放热装置中。 因此，钛酸钡半导体陶瓷使得能够使用其的装置具有增强的性能和减小的尺寸。