公开(公告)号：US06418075B2

公开(公告)日：2002-07-09

申请号：US09759315

申请日：2001-01-16

申请人： Hiroki Shimano ,  Kazutami Arimoto ,  Yasuhiro Ishizuka ,  Seizou Furubeppu ,  Hiroki Sugano

发明人： Hiroki Shimano ,  Kazutami Arimoto ,  Yasuhiro Ishizuka ,  Seizou Furubeppu ,  Hiroki Sugano

IPC分类号： G11C514

CPC分类号： G11C5/145 ,  G11C5/14 ,  G11C5/147

摘要： A semiconductor integrated circuit in which a logic and a memory are merged, includes a voltage generation unit for generating two or more internal power supply voltages based on two or more external power supply voltages supplied from outside the voltage generation unit with different timings and for furnishing the plurality of internal power supply voltages to the memory. The voltage generation unit includes a standby unit with a small current-feed ability that is always activated, for generating the plurality of internal power supply voltages, and an active unit with a large current-feed ability that is activated as needed, for generating the plurality of internal power supply voltages. An activation control unit prevents the active unit from being activated until all of the plurality of external power supply voltages rise.

摘要翻译： 其中逻辑和存储器被合并的半导体集成电路包括：电压产生单元，用于基于从电压产生单元的外部以不同的定时提供的两个或多个外部电源电压产生两个或多个内部电源电压， 将多个内部电源电压提供给存储器。 电压产生单元包括：始终激活的小电流馈送能力的待机单元，用于产生多个内部电源电压;以及具有大电流馈送能力的有源单元，其根据需要被激活，用于产生 多个内部电源电压。 激活控制单元防止有效单元在所有多个外部电源电压升高之前被激活。

公开(公告)号：US06400625B2

公开(公告)日：2002-06-04

申请号：US09810503

申请日：2001-03-19

申请人： Kazutami Arimoto ,  Hiroki Shimano ,  Katsumi Dosaka

发明人： Kazutami Arimoto ,  Hiroki Shimano ,  Katsumi Dosaka

IPC分类号： G11C700

CPC分类号： G11C29/48

摘要： A test interface circuit carries out an operational test based on a signal input to test pin terminals by directly accessing a DRAM core. A frequency multiplication circuit generates an internal test clock signal by multiplying the frequency of an external test clock signal input to the test pin terminal. A data shifter shifts read data from the DRAM core which operates according to the internal test clock signal in a test mode by N clock cycles (N is an integer of at least 0 determined by column latency) of the internal test clock signal to output the read data from the test pin terminals in synchronization with the external clock test signal.

摘要翻译： 测试接口电路基于通过直接访问DRAM内核来测试引脚端子的信号输入进行操作测试。 倍频电路通过将输入到测试引脚端子的外部测试时钟信号的频率相乘来生成内部测试时钟信号。 数据移位器根据内部测试时钟信号在内部测试时钟信号的N个时钟周期（N为至少为0的整数，由列延迟确定）中，根据测试模式的内部测试时钟信号来移动读取数据，以输出 从外部时钟测试信号同步读取测试引脚端子的数据。

公开(公告)号：US06256252B1

公开(公告)日：2001-07-03

申请号：US09659552

申请日：2000-09-11

申请人： Kazutami Arimoto

发明人： Kazutami Arimoto

IPC分类号： G11C700

CPC分类号： G11C7/22 ,  G11C11/4076 ,  G11C2207/104

摘要： In a sleep mode, data held in a logic circuit is saved to a memory circuit under the control of a transfer control circuit, and thereafter supply of an operation power supply voltage to the logic circuit from a logic power source is stopped. A memory-embedded LSI capable of reducing current consumption in a standby state is provided.

摘要翻译： 在睡眠模式下，保持在逻辑电路中的数据在转移控制电路的控制下被保存到存储器电路，然后停止从逻辑电源向逻辑电路提供操作电源电压。 提供了能够在待机状态下降低电流消耗的存储器嵌入式LSI。

公开(公告)号：US6157052A

公开(公告)日：2000-12-05

申请号：US174315

申请日：1998-10-19

申请人： Shigehiro Kuge ,  Kazutami Arimoto

发明人： Shigehiro Kuge ,  Kazutami Arimoto

IPC分类号： H01L21/822 ,  G11C11/401 ,  H01L21/82 ,  H01L21/8242 ,  H01L23/528 ,  H01L27/04 ,  H01L27/108 ,  H01L27/10

CPC分类号： H01L23/528 ,  H01L27/10805 ,  H01L2924/0002 ,  H01L2924/3011 ,  Y10S257/903

摘要： A high melting point metal wiring layer, a second aluminum wiring layer, and a third aluminum wiring layer are stacked on transistors forming an inverter train of a hierarchical power supply structure respectively. The high melting point metal wiring layer is employed as a local wire for connecting the transistors with each other, the second aluminum wiring layer is employed as a local bus wire and a hierarchical power supply wire, and the third aluminum wiring layer is employed as a main bus wire and a power supply wire to intersect with the respective wires. Consequently, the wiring layers are easy to lay out, while no main bus region is required dissimilarly to the prior art and it is possible to reduce the layout area.

公开(公告)号：US5982678A

公开(公告)日：1999-11-09

申请号：US882758

申请日：1997-06-26

申请人： Tsukasa Ooishi ,  Yoshio Matsuda ,  Kazutami Arimoto ,  Masaki Tsukude ,  Kazuyasu Fujishima

发明人： Tsukasa Ooishi ,  Yoshio Matsuda ,  Kazutami Arimoto ,  Masaki Tsukude ,  Kazuyasu Fujishima

IPC分类号： G11C11/413 ,  G11C7/00 ,  G11C11/401 ,  G11C29/00 ,  G11C29/04 ,  H01L21/82 ,  H01L27/10

CPC分类号： G11C29/806 ,  G11C29/781 ,  G11C8/10

摘要： A semiconductor memory device comprises two memory cell arrays (1a, 1b) in which a block divisional operation is performed. Two spare rows (2a, 2b) are provided corresponding to the two memory cell arrays (1a, 1b). Spare row decoders (5a, 5b) are provided for selecting the spare rows (2a, 2b), respectively. One spare row decoder selecting signal generation circuit (18) used in common by the spare row decoders (5a, 5b) is provided. The spare row decoder selecting signal generation circuit (18) can be previously set so as to generate a spare row decoder selecting signal (SRE) when a defective row exists in either of the memory cell arrays (1a, 1b) and the defective row is selected by row decoder groups (4a, 4b). Each of the spare row decoders (5a, 5b) is activated in response to the spare row decoder selecting signal (SRE) and a block control signal.

公开(公告)号：US5969420A

公开(公告)日：1999-10-19

申请号：US881397

申请日：1997-06-24

申请人： Shigehiro Kuge ,  Kazutami Arimoto ,  Masaki Tsukude ,  Kazuyasu Fujishima

发明人： Shigehiro Kuge ,  Kazutami Arimoto ,  Masaki Tsukude ,  Kazuyasu Fujishima

IPC分类号： H01L21/28 ,  H01L21/3205 ,  H01L21/768 ,  H01L21/82 ,  H01L21/822 ,  H01L21/8242 ,  H01L23/52 ,  H01L23/522 ,  H01L23/528 ,  H01L25/04 ,  H01L25/18 ,  H01L27/02 ,  H01L27/04 ,  H01L27/108 ,  H01L23/48

CPC分类号： H01L23/5286 ,  H01L27/0207 ,  H01L27/10897 ,  H01L2924/0002 ,  H01L2924/3011

摘要： On transistors P1, P2, N1 and N2 constituting an NAND gate, interconnection pattern W of metal having high melting point and aluminum interconnection patterns Al1 and Al2 are stacked. A local line LL for connecting transistors P1, P2, N1 and N2 to each other is formed by the interconnection pattern W of metal having high melting point, signal lines SL and SL' for signal input/output between the NAND gate and the outside are formed by aluminum interconnection pattern Al1, and power supply lines VL and VL' for applying power supply potentials Vcc and Vss to the NAND gate are formed by the aluminum interconnection pattern Al2. As compared with the prior art in which the local line LL is formed by the aluminum interconnection pattern Al1, the degree of freedom in layout can be improved and the layout area can be reduced.

摘要翻译： 在构成NAND门的晶体管P1，P2，N1和N2上，堆叠具有高熔点金属的互连图案W和铝互连图案Al1和Al2。 用于将晶体管P1，P2，N1和N2相互连接的本地线路LL通过具有高熔点金属的互连图形W，在与非门与外部之间的信号输入/输出的信号线SL和SL'形成 由铝互连图案Al1形成，并且用于将电源电位Vcc和Vss施加到NAND门的电源线VL和VL'由铝互连图案Al2形成。 与通过铝互连图案Al1形成局部线LL的现有技术相比，可以提高布局的自由度，并且可以减小布局面积。

公开(公告)号：US5909046A

公开(公告)日：1999-06-01

申请号：US965618

申请日：1997-11-06

申请人： Tetsushi Tanizaki ,  Fukashi Morishita ,  Masaki Tsukude ,  Kazutami Arimoto

发明人： Tetsushi Tanizaki ,  Fukashi Morishita ,  Masaki Tsukude ,  Kazutami Arimoto

IPC分类号： H01L27/04 ,  H01L21/822 ,  H01L27/02 ,  H01L23/62

CPC分类号： H01L27/0248 ,  H01L24/05 ,  H01L2924/14

摘要： A conductor line is placed at a layer overlying an input protection circuit electrically coupled to a pad such that the conductor line covers at least a part of the input protection circuit. The conductor line having a sufficiently large width disperses and absorbs the heat generated from the input protection circuit. Since the input protection circuit and the conductor line have a region overlapping with each other in the layout of plan view, an area for layout of the input protection circuit on a chip can be reduced effectively, and prevention of a destruction of the protection circuit due to the heat as well as an improvement of a resistance to the surge can be obtained.

摘要翻译： 导体线被放置在覆盖输入保护电路的层上，该输入保护电路电耦合到焊盘，使得导线覆盖输入保护电路的至少一部分。 具有足够大的宽度的导体线分散并吸收从输入保护电路产生的热量。 由于输入保护电路和导体线在平面图的布局中具有彼此重叠的区域，因此可以有效地降低芯片上的输入保护电路布局的区域，并防止保护电路的破坏 可以获得耐热性，并且可以获得耐喘振性的改善。

公开(公告)号：US5726943A

公开(公告)日：1998-03-10

申请号：US583810

申请日：1996-01-05

申请人： Tadato Yamagata ,  Kazutami Arimoto

发明人： Tadato Yamagata ,  Kazutami Arimoto

IPC分类号： G11C7/06 ,  G11C11/406 ,  G11C11/409 ,  G11C11/4091 ,  G11C7/00 ,  G11C7/02 ,  G11C8/00

CPC分类号： G11C11/4091 ,  G11C11/406 ,  G11C7/065

摘要： A memory cell array of a dynamic semiconductor memory device is divided into a plurality of memory cell blocks. A block selecting circuit selects and refreshes larger number of memory cell blocks in refreshing mode than the number of those selected during normal mode. Sense amplifiers in the memory cell blocks selected by the block selecting circuit are selectively driven with smaller driving force in refreshing mode than that in normal mode. More preferably the driving force is changed during the amplifying operation so as to achieve both the high sensitivity and the suppression of the peak value of the operational current.

摘要翻译： 动态半导体存储器件的存储单元阵列被分成多个存储单元块。 块选择电路在更新模式下选择和刷新大量的在正常模式下选择的存储单元块的数量。 通过块选择电路选择的存储单元块中的感测放大器在刷新模式下以比正常模式更小的驱动力被选择性地驱动。 更优选地，在放大操作期间驱动力被改变，以便实现操作电流的峰值的高灵敏度和抑制。

公开(公告)号：US5375088A

公开(公告)日：1994-12-20

申请号：US149540

申请日：1993-11-09

申请人： Kiyohiro Furutani ,  Koichiro Mashiko ,  Kazutami Arimoto ,  Noriaki Matsumoto ,  Yoshio Matsuda

发明人： Kiyohiro Furutani ,  Koichiro Mashiko ,  Kazutami Arimoto ,  Noriaki Matsumoto ,  Yoshio Matsuda

IPC分类号： G06F11/267 ,  G11C7/10 ,  G11C29/26 ,  G11C29/38 ,  G11C7/00

CPC分类号： G11C7/10 ,  G11C29/26 ,  G11C29/38 ,  G11C7/1006 ,  G11C7/1051 ,  G11C7/1057 ,  G11C7/1078 ,  G11C7/1084 ,  G06F11/267

摘要： A semiconductor memory device operable for reading and writing in a normal mode and in a test mode is divided into memory cell sections each having blocks of memory cells. Data bus lines are connected to the respective blocks, and switches interconnect data bus lines connected to blocks of the different sections. The switch are made conductive during reading and writing in the normal mode and during writing in the test mode, and nonconductive during reading in the test mode. Input data are applied onto the data bus lines connected to one of the blocks for writing in the blocks of the sections simultaneously during writing in the normal mode and in the test mode. In the normal mode, data are read out of the blocks of the sections through the data bus lines connected to the above-mentioned one of the blocks. In the test mode, the data are read out of the blocks of the sections through the data bus lines connected to the respective blocks.

摘要翻译： 可以以正常模式和测试模式读取和写入的半导体存储器件被分成具有存储单元块的存储单元部分。 数据总线连接到相应的块，并且交换连接到不同部分的块的数据总线。 在正常模式下读写时，在测试模式下写入期间开关导通，在测试模式下读取期间不导通。 在正常模式和测试模式下，输入数据被施加到连接到块之一的数据总线上，用于在写入期间同时在块中写入。 在正常模式下，通过连接到上述一个块的数据总线，从这些部分的块中读出数据。 在测试模式中，通过连接到相应块的数据总线，从这些部分的块中读出数据。

公开(公告)号：US5132930A

公开(公告)日：1992-07-21

申请号：US577062

申请日：1990-09-04

申请人： Kiyohiro Furutani ,  Koichiro Mashiko ,  Kazutami Arimoto ,  Noriaki Matsumoto ,  Yoshio Matsuda

发明人： Kiyohiro Furutani ,  Koichiro Mashiko ,  Kazutami Arimoto ,  Noriaki Matsumoto ,  Yoshio Matsuda

IPC分类号： G11C11/4091 ,  G11C11/4097

CPC分类号： G11C11/4097 ,  G11C11/4091

摘要： In a metal-oxide semiconductor (MOS) dynamic formed on a semiconductor substrate, data nodes of a first flip-flop are connected to a first pair of folded bit lines. Its power supply node is connected through a switch to a first power supply (Vss). Data nodes of a second flip-flop are connected to a second pair of folded bit lines. Its power supply node is connected through a switch to the first power supply (Vss). A power supply node of a third flip-flop is connected through a switch to a second power supply (Vcc). Data nodes of the third flip-flop are coupled through a first pair of transfer gates to the first pair of the folded bit lines, and through a second pair of transfer gates to the second pair of the folded bit lines. Coupling the first to the third flip-flops forms a first sense amplifier and coupling the second to the third flip-flops forms a second sense amplifier.

摘要翻译： 在半导体衬底上形成的金属氧化物半导体（MOS）动态中，第一触发器的数据节点连接到第一对折叠位线。 其电源节点通过开关连接到第一电源（Vss）。 第二触发器的数据节点连接到第二对折叠位线。 其电源节点通过开关连接到第一电源（Vss）。 第三触发器的电源节点通过开关连接到第二电源（Vcc）。 第三触发器的数据节点通过第一对传输门耦合到第一对折叠位线，并通过第二对传输门耦合到第二对折叠位线。 耦合第一至第三触发器形成第一读出放大器并且将第二触发器耦合到第三触发器形成第二读出放大器。