公开(公告)号：US20090026497A1

公开(公告)日：2009-01-29

申请号：US11988305

申请日：2006-06-26

申请人： Yoshio Shimoida ,  Hideaki Tanaka ,  Tetsuya Hayashi ,  Masakatsu Hoshi ,  Shigeharu Yamagami ,  Noriaki Kawamoto ,  Takayuki Kitou ,  Mineo Miura ,  Takashi Nakamura

发明人： Yoshio Shimoida ,  Hideaki Tanaka ,  Tetsuya Hayashi ,  Masakatsu Hoshi ,  Shigeharu Yamagami ,  Noriaki Kawamoto ,  Takayuki Kitou ,  Mineo Miura ,  Takashi Nakamura

IPC分类号： H01L21/336 ,  H01L29/78

CPC分类号： H01L21/049 ,  H01L29/1608 ,  H01L29/267 ,  H01L29/66068 ,  H01L29/772 ,  H01L29/7828

摘要： A method for producing a semiconductor device (20) is disclosed. The semiconductor device (20) includes: 1) a semiconductor substrate (1, 2), 2) a hetero semiconductor area (3) configured to contact a first main face (1A) of the semiconductor substrate (1, 2) and different from the semiconductor substrate (1, 2) in band gap, 3) a gate electrode (7) contacting, via a gate insulating film (6), a part of a junction part (13) between the hetero semiconductor area (3) and the semiconductor substrate (1, 2), 4) a source electrode (8) configured to connect to the hetero semiconductor area (3), and 5) a drain electrode (9) configured to make an ohmic connection with the semiconductor substrate (1, 2). The method includes the following sequential operations: i) forming the gate insulating film (6); and ii) nitriding the gate insulating film (6).

摘要翻译： 公开了一种用于制造半导体器件（20）的方法。 半导体器件（20）包括：1）半导体衬底（1,2），2）异质半导体区域（3），被配置为接触半导体衬底（1,2）的第一主面（1A） 所述半导体衬底（1,2）具有带隙，3）栅极电极（7）经由栅极绝缘膜（6）与所述异质半导体区域（3）之间的接合部分（13）的一部分 半导体衬底（1,2），4）构造成连接到所述异质半导体区域（3）的源电极（8），以及5）被配置为与所述半导体衬底（1,2）形成欧姆连接的漏电极（9） 2）。 该方法包括以下顺序操作：i）形成栅极绝缘膜（6）; 和ii）氮化所述栅极绝缘膜（6）。

公开(公告)号：US20070252172A1

公开(公告)日：2007-11-01

申请号：US11741305

申请日：2007-04-27

申请人： Tetsuya Hayashi ,  Masakatsu Hoshi ,  Yoshio Shimoida ,  Hideaki Tanaka ,  Shigeharu Yamagami

发明人： Tetsuya Hayashi ,  Masakatsu Hoshi ,  Yoshio Shimoida ,  Hideaki Tanaka ,  Shigeharu Yamagami

IPC分类号： H01L31/00

CPC分类号： H01L29/7828 ,  H01L29/0623 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/1608 ,  H01L29/267 ,  H01L29/36 ,  H01L29/4236 ,  H01L29/45 ,  H01L29/456 ,  H01L29/8618

摘要： A semiconductor device, includes: 1) a semiconductor base having a first face; 2) a hetero semiconductor region configured to contact the first face of the semiconductor base and different from the semiconductor base in band gap, the semiconductor base and the hetero semiconductor region defining therebetween a junction part in the hetero semiconductor region, a concentration of an impurity introduced in at least a first certain region including the junction part being less than or equal to a solid solution limit to a semiconductor material included in the hetero semiconductor region; 3) a gate electrode formed, via a gate insulation film, in a certain position adjacent to the junction part; 4) a source electrode configured to be connected to the hetero semiconductor region; and 5) a drain electrode configured to be connected to the semiconductor base.

摘要翻译： 一种半导体器件，包括：1）具有第一面的半导体基底; 2）异质半导体区域，被配置为在带隙中接触半导体基底的第一面并且不同于半导体基底，半导体基底和异质半导体区域在其间限定异质半导体区域中的接合部分，杂质浓度 引入至少包括所述接合部分的第一特定区域小于或等于包含在所述异质半导体区域中的半导体材料的固溶极限; 3）通过栅极绝缘膜在与所述接合部分相邻的特定位置处形成的栅电极; 4）构造成连接到所述异质半导体区域的源电极; 以及5）被配置为连接到所述半导体基底的漏电极。

公开(公告)号：US20070221955A1

公开(公告)日：2007-09-27

申请号：US11724389

申请日：2007-03-15

申请人： Yoshio Shimoida ,  Tetsuya Hayashi ,  Hideaki Tanaka ,  Shigeharu Yamagami ,  Masakatsu Hoshi

发明人： Yoshio Shimoida ,  Tetsuya Hayashi ,  Hideaki Tanaka ,  Shigeharu Yamagami ,  Masakatsu Hoshi

IPC分类号： H01L29/739

CPC分类号： H01L29/7828 ,  H01L21/0273 ,  H01L21/32139 ,  H01L29/1608 ,  H01L29/267 ,  H01L29/4236 ,  H01L29/66068

摘要： A trench is formed extending from a surface of a hetero semiconductor region of a polycrystal silicon to the drain region. Further, a driving point of the field effect transistor, where a gate insulating film, the hetero semiconductor region and the drain region are adjoined, is formed at a position spaced apart from a side wall of the trench.

摘要翻译： 形成从多晶硅的异质半导体区域的表面延伸到漏极区域的沟槽。 此外，栅极绝缘膜，异质半导体区域和漏极区域相邻的场效应晶体管的驱动点形成在与沟槽的侧壁间隔开的位置处。

公开(公告)号：US20070181886A1

公开(公告)日：2007-08-09

申请号：US11701429

申请日：2007-02-02

申请人： Yoshio Shimoida ,  Masakatsu Hoshi ,  Tetsuya Hayashi ,  Hideaki Tanaka ,  Shigeharu Yamagami

发明人： Yoshio Shimoida ,  Masakatsu Hoshi ,  Tetsuya Hayashi ,  Hideaki Tanaka ,  Shigeharu Yamagami

IPC分类号： H01L31/0312

CPC分类号： H01L29/267 ,  H01L29/0619 ,  H01L29/0623 ,  H01L29/0696 ,  H01L29/1608 ,  H01L29/66068 ,  H01L29/7828

摘要： A semiconductor device, includes: a first conductivity-semiconductor substrate; a hetero semiconductor region for forming a hetero junction with the first conductivity-semiconductor substrate; a gate electrode adjacent to a part of the hetero junction by way of a gate insulating film; a drain electrode connecting to the first conductivity-semiconductor substrate; a source electrode connecting to the hetero semiconductor region; and a second conductivity-semiconductor region formed on a part of a first face of the first conductivity-semiconductor substrate in such a configuration as to oppose the gate electrode via the gate insulating film, the gate insulating film, the hetero semiconductor region and the first conductivity-semiconductor substrate contacting each other to thereby form a triple contact point. A first face of the second conductivity-semiconductor region has such an impurity concentration that allows a field from the gate electrode to form an inversion layer on the first face of the second conductivity-semiconductor region.

摘要翻译： 一种半导体器件，包括：第一导电半导体衬底; 用于与第一导电半导体衬底形成异质结的异质半导体区域; 通过栅绝缘膜与所述异质结的一部分相邻的栅电极; 连接到所述第一导电半导体衬底的漏电极; 连接到所述异质半导体区域的源电极; 以及第二导电半导体区域，形成在第一导电半导体基板的第一面的一部分上，以与栅电极相对的方式经由栅极绝缘膜，栅极绝缘膜，异质半导体区域和第一导电半导体区域 导电性半导体基板彼此接触，从而形成三重接触点。 第二导电率半导体区域的第一面具有允许来自栅电极的场在第二导电半导体区域的第一面上形成反型层的杂质浓度。

公开(公告)号：US07531396B2

公开(公告)日：2009-05-12

申请号：US11374418

申请日：2006-03-14

申请人： Tetsuya Hayashi ,  Masakatsu Hoshi ,  Yoshio Shimoida ,  Hideaki Tanaka

发明人： Tetsuya Hayashi ,  Masakatsu Hoshi ,  Yoshio Shimoida ,  Hideaki Tanaka

IPC分类号： H01L21/338 ,  H01L21/066

CPC分类号： H01L29/66068 ,  H01L21/8213 ,  H01L29/0619 ,  H01L29/0623 ,  H01L29/0847 ,  H01L29/1608 ,  H01L29/267 ,  H01L29/41741 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/7828

摘要： A method of manufacturing a semiconductor device is disclosed. The semiconductor device includes a semiconductor body of a first conductivity type, a hetero semiconductor region adjacent to one main surface of the semiconductor body and having a band gap different from that of the semiconductor body, and a gate electrode formed in a junction portion between the hetero semiconductor region and the semiconductor body through a gate insulating film. The method includes a first process of forming a predetermined trench by using a mask layer having a predetermined opening on one main surface side of the semiconductor body, a second process of forming a buried region adjacent to at least a side wall of the trench and so as to extend from the trench, a third process of forming a hetero semiconductor layer so as to adjoin the semiconductor body and the buried region, and a fourth process of forming the hetero semiconductor region by patterning the hetero semiconductor layer.

摘要翻译： 公开了制造半导体器件的方法。 半导体器件包括第一导电类型的半导体本体，与半导体本体的一个主表面相邻且具有与半导体本体不同的带隙的异质半导体区域，以及形成在该半导体器件之间的接合部分中的栅电极 异质半导体区域和半导体本体通过栅极绝缘膜。 该方法包括通过使用在半导体主体的一个主表面侧上具有预定开口的掩模层来形成预定沟槽的第一工艺，形成与沟槽的至少侧壁相邻的掩埋区域的第二工艺 从沟槽延伸，形成与半导体本体和掩埋区相邻的异质半导体层的第三工序，以及通过图案化杂半导体层形成异质半导体区的第四工序。

公开(公告)号：US07183575B2

公开(公告)日：2007-02-27

申请号：US10368016

申请日：2003-02-19

申请人： Yoshio Shimoida ,  Saichirou Kaneko ,  Hideaki Tanaka ,  Masakatsu Hoshi ,  Kraisom Throngnumchai ,  Teruyoshi Mihara ,  Tetsuya Hayashi

发明人： Yoshio Shimoida ,  Saichirou Kaneko ,  Hideaki Tanaka ,  Masakatsu Hoshi ,  Kraisom Throngnumchai ,  Teruyoshi Mihara ,  Tetsuya Hayashi

IPC分类号： H01L29/15

CPC分类号： H01L29/267 ,  H01L29/1608 ,  H01L29/861

摘要： A high reverse voltage diode includes a hetero junction made up from a silicon carbide base layer, which constitutes a first semiconductor base layer, and a polycrystalline silicon layer, which constitutes a second semiconductor layer, and whose band gap is different from that of the silicon carbide base layer. A low concentration N type polycrystalline silicon layer is deposited on a first main surface side of the silicon carbide base layer, and a metal electrode is formed on a second main surface side of the silicon carbide base layer which is opposite to the first main surface side thereof.

摘要翻译： 高反向电压二极管包括由构成第一半导体基底层的碳化硅基底层和构成第二半导体层的多晶硅层构成的异质结，并且其带隙与硅的带隙不同 碳化物基层。 在碳化硅基底层的第一主表面侧沉积低浓度N型多晶硅层，在与第一主表面侧相反的碳化硅基底层的第二主表面侧上形成金属电极 其中。

公开(公告)号：US07476590B2

公开(公告)日：2009-01-13

申请号：US11231799

申请日：2005-09-22

申请人： Tetsuya Hayashi ,  Masakatsu Hoshi ,  Yoshio Shimoida ,  Hideaki Tanaka

发明人： Tetsuya Hayashi ,  Masakatsu Hoshi ,  Yoshio Shimoida ,  Hideaki Tanaka

IPC分类号： H01L21/336

CPC分类号： H01L29/7828 ,  H01L29/1608 ,  H01L29/267 ,  H01L29/66068 ,  H01L29/7827

摘要： A method of manufacturing a semiconductor device having: forming a hetero semiconductor layer on at least the major surface of the semiconductor substrate body of a first conductivity type; etching the hetero semiconductor layer selectively by use of a mask layer having openings in way that the hetero semiconductor layer remains to be not etched with a predetermined thickness; oxidizing an exposed parts of the hetero semiconductor layer; forming the hetero semiconductor region by etching a oxidized film formed in the oxidizing; and forming the gate insulating film in a way that the gate insulating film makes an intimate contact with the hetero semiconductor region and the semiconductor substrate body. The bandgap of the hetero semiconductor layer is different from that of the semiconductor substrate body. The gate electrode is arranged in a junction part between the hetero semiconductor region and the semiconductor substrate body with the gate insulating film interposed between the gate electrode and the junction part.

摘要翻译： 一种制造半导体器件的方法，其特征在于：在至少在第一导电类型的半导体衬底主体的主表面上形成杂半导体层; 通过使用具有开口的掩模层选择性地蚀刻异质半导体层，使得异质半导体层保持不被预定厚度蚀刻; 氧化杂半导体层的暴露部分; 通过蚀刻氧化膜形成的氧化膜来形成异质半导体区域; 以及栅极绝缘膜与异质半导体区域和半导体衬底本体紧密接触的方式形成栅极绝缘膜。 异质半导体层的带隙与半导体衬底本体的带隙不同。 栅电极配置在异质半导体区域和半导体衬底本体之间的接合部分中，栅极绝缘膜介于栅电极和接合部分之间。

公开(公告)号：US20060068537A1

公开(公告)日：2006-03-30

申请号：US11231799

申请日：2005-09-22

申请人： Tetsuya Hayashi ,  Masakatsu Hoshi ,  Yoshio Shimoida ,  Hideaki Tanaka

发明人： Tetsuya Hayashi ,  Masakatsu Hoshi ,  Yoshio Shimoida ,  Hideaki Tanaka

IPC分类号： H01L21/8234 ,  H01L21/336

CPC分类号： H01L29/7828 ,  H01L29/1608 ,  H01L29/267 ,  H01L29/66068 ,  H01L29/7827

摘要： A method of manufacturing a semiconductor device having: forming a hetero semiconductor layer on at least the major surface of the semiconductor substrate body of a first conductivity type; etching the hetero semiconductor layer selectively by use of a mask layer having openings in way that the hetero semiconductor layer remains to be not etched with a predetermined thickness; oxidizing an exposed parts of the hetero semiconductor layer; forming the hetero semiconductor region by etching a oxidized film formed in the oxidizing; and forming the gate insulating film in a way that the gate insulating film makes an intimate contact with the hetero semiconductor region and the semiconductor substrate body. The bandgap of the hetero semiconductor layer is different from that of the semiconductor substrate body. The gate electrode is arranged in a junction part between the hetero semiconductor region and the semiconductor substrate body with the gate insulating film interposed between the gate electrode and the junction part.

公开(公告)号：US07807534B2

公开(公告)日：2010-10-05

申请号：US12033468

申请日：2008-02-19

申请人： Hideaki Tanaka ,  Masakatsu Hoshi ,  Tetsuya Hayashi ,  Shigeharu Yamagami

发明人： Hideaki Tanaka ,  Masakatsu Hoshi ,  Tetsuya Hayashi ,  Shigeharu Yamagami

IPC分类号： H01L29/76

CPC分类号： H01L29/0847 ,  H01L29/1608 ,  H01L29/267 ,  H01L29/66068 ,  H01L29/7828

摘要： A method for producing a semiconductor device includes forming a first hetero-semiconductor layer as a hetero-junction to a surface of a silicon carbide epitaxial layer. This layer is composed of polycrystalline silicon having a band gap different from that of the silicon carbide epitaxial layer. An etching stopper layer composed of a material having a different etching rate from that of the polycrystalline silicon is formed on the surface of the first hetero-semiconductor layer. A second hetero-semiconductor layer composed of polycrystalline silicon is formed so that the second hetero-semiconductor layer contacts the surface of the first hetero-semiconductor layer and the etching stopper layer. The etching stopper layer is removed, the first hetero-semiconductor layer is thermally oxidized, and the thermally oxidized portion is then removed.

摘要翻译： 一种制造半导体器件的方法包括：将第一异质半导体层形成为与碳化硅外延层的表面的异质结。 该层由具有与碳化硅外延层的带隙不同的带隙的多晶硅构成。 在第一异质半导体层的表面上形成由具有与多晶硅的蚀刻速率不同的蚀刻速率的材料构成的蚀刻停止层。 形成由多晶硅构成的第二异质半导体层，使得第二异质半导体层与第一异质半导体层和蚀刻停止层的表面接触。 除去蚀刻停止层，将第一异质半导体层热氧化，然后除去热氧化部分。

公开(公告)号：US20090140264A1

公开(公告)日：2009-06-04

申请号：US12325377

申请日：2008-12-01

申请人： Tetsuya Hayashi ,  Masakatsu Hoshi ,  Hideaki Tanaka ,  Shigeharu Yamagami

发明人： Tetsuya Hayashi ,  Masakatsu Hoshi ,  Hideaki Tanaka ,  Shigeharu Yamagami

IPC分类号： H01L29/24 ,  H01L29/78

CPC分类号： H01L29/0847 ,  H01L29/0623 ,  H01L29/0642 ,  H01L29/0646 ,  H01L29/0649 ,  H01L29/0696 ,  H01L29/1608 ,  H01L29/267 ,  H01L29/7828

摘要： A hetero semiconductor corner region, which is a current-concentration relief region that keeps a reverse bias current from concentrating on the convex corner, is arranged in a hetero semiconductor region. Thereby, a current concentration on the convex corner can be prevented. As a result, an interrupting performance can be improved at the time of interruption, and at the same time, the generation of the hot spot where in a specific portion is prevented at the time of conduction to suppress deterioration in a specific portion, thereby ensuring a long-term reliability. Further, when the semiconductor chip is used in an L load circuit or the like, for example, at the time of conduction or during a transient response time to the interrupted state, in an index such as a short resistant load amount and an avalanche resistant amount, which are indexes of a breakdown tolerance when overcurrent or overvoltage occurs, the current concentration on a specific portion can be prevented, and thus, these breakdown tolerances can also be improved.

摘要翻译： 作为将反向偏置电流保持集中在凸角上的电流 - 浓度释放区域的异质半导体角区域设置在异质半导体区域中。 由此，可以防止凸角上的电流集中。 结果，在中断时可以提高中断性能，同时，在导通时防止特定部位的热点的产生，抑制特定部分的劣化，从而确保 长期可靠。 此外，例如在导通时或半导体芯片用于L负载电路等时，例如，在短时间响应时间到中断状态时，以诸如短路负载量和雪崩阻抗的指标 量是当发生过电流或过电压时的击穿容限的指标，可以防止特定部分上的电流浓度，因此也可以提高这些击穿公差。