公开(公告)号：US20060239072A1

公开(公告)日：2006-10-26

申请号：US11472993

申请日：2006-06-23

申请人： Toshihiro Tanaka ,  Takashi Yamaki ,  Yutaka Shinagawa ,  Daisuke Okada ,  Digh Hisamoto ,  Kan Yasui ,  Tetsuya Ishimaru

发明人： Toshihiro Tanaka ,  Takashi Yamaki ,  Yutaka Shinagawa ,  Daisuke Okada ,  Digh Hisamoto ,  Kan Yasui ,  Tetsuya Ishimaru

IPC分类号： G11C16/04 ,  G11C11/34

CPC分类号： G11C16/10 ,  G11C16/0433

摘要： Disclosed here is a method for speeding up data writing and reducing power consumption by reducing the variation of the threshold voltage of each of non-volatile memory cells at data writing. When writing data in a memory cell, a voltage of about 8V is applied to the memory gate line, a voltage of about 5V is applied to the source line, a voltage of about 1.5V is applied to the selected gate line respectively. At that time, in the writing circuit, the writing pulse is 0, the writing latch output a High signal, and a NAND-circuit outputs a Low signal. And, a constant current of about 1 iA flows in a constant current source transistor and the bit line is discharged by a constant current of about 1 iA to flow a current in the memory cell.

摘要翻译： 这里公开了一种通过在数据写入时减小每个非易失性存储单元的阈值电压的变化来加速数据写入并降低功耗的方法。 当在存储单元中写入数据时，约8V的电压被施加到存储器栅极线，大约5V的电压被施加到源极线，大约1.5V的电压分别施加到所选择的栅极线。 此时，在写入电路中，写入脉冲为0，写入锁存器输出高电平信号，NAND电路输出低电平信号。 并且，在恒定电流源晶体管中流动约1IA的恒定电流，并且通过约1iA的恒定电流放电位线以使存储单元中的电流流动。

公开(公告)号：US20060035435A1

公开(公告)日：2006-02-16

申请号：US11189078

申请日：2005-07-26

申请人： Kan Yasui ,  Digh Hisamoto ,  Tetsuya Ishimaru

发明人： Kan Yasui ,  Digh Hisamoto ,  Tetsuya Ishimaru

IPC分类号： H01L21/336

CPC分类号： H01L29/792 ,  G11C16/0466 ,  H01L27/115 ,  H01L27/11519 ,  H01L27/11568 ,  H01L29/42344

摘要： Semiconductor device and manufacturing method for reducing the number of required lithography masks added to the nonvolatile memory in the standard CMOS process to shorten the production period and reduce costs. In a split-gate memory cell with silicided gate electrodes utilizing a sidewall structure, a separate auxiliary pattern is formed adjoining the selected gate electrodes. A contact is set on a wiring layer self-aligned by filling side-wall gates of polysilicon in the gap between the electrodes and auxiliary pattern. The contact may overlap onto the auxiliary pattern and device isolation region, in an optimal design considering the size of the occupied surface area. If the distance to the selected gate electrode is x, the ONO film deposit thickness is t, and the polysilicon film deposit thickness is d, then the auxiliary pattern may be separated just by a distance x such that x

摘要翻译： 用于减少在标准CMOS工艺中添加到非易失性存储器中的所需光刻掩模的数量的半导体器件和制造方法，以缩短生产周期并降低成本。 在具有利用侧壁结构的硅化栅电极的分裂栅极存储单元中，形成邻接所选择的栅电极的单独的辅助图案。 通过填充电极和辅助图案之间的间隙中的多晶硅的侧壁栅极，将接触设置在自对准的布线层上。 考虑到占用的表面积的大小，接触可以以最佳设计重叠在辅助图案和设备隔离区域上。 如果到选定的栅电极的距离为x，则ONO膜沉积厚度为t，多晶硅膜沉积厚度为d，则辅助图案可以仅分开距离x，使得x <2x（t + d） 。

公开(公告)号：US20060022260A1

公开(公告)日：2006-02-02

申请号：US11182013

申请日：2005-07-15

申请人： Digh Hisamoto ,  Kan Yasui ,  Shinichiro Kimura ,  Tetsuya Ishimaru

发明人： Digh Hisamoto ,  Kan Yasui ,  Shinichiro Kimura ,  Tetsuya Ishimaru

IPC分类号： H01L29/792 ,  H01L21/336

CPC分类号： H01L27/11568 ,  G11C16/0433 ,  H01L21/2815 ,  H01L21/28273 ,  H01L21/28282 ,  H01L21/84 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/1203 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/792

摘要： Provided is a nonvolatile semiconductor memory device having a split gate structure, wherein a memory gate is formed over a convex shaped substrate and side surfaces of it is used as a channel. The nonvolatile semiconductor memory device according to the present invention is excellent in read current driving power even if a memory cell is scaled down.

公开(公告)号：US20100232231A1

公开(公告)日：2010-09-16

申请号：US12787158

申请日：2010-05-25

申请人： Digh HISAMOTO ,  Kan Yasui ,  Tetsuya Ishimaru ,  Shinichiro Kimura ,  Daisuke Okada

发明人： Digh HISAMOTO ,  Kan Yasui ,  Tetsuya Ishimaru ,  Shinichiro Kimura ,  Daisuke Okada

IPC分类号： G11C16/06 ,  G11C11/34

CPC分类号： G11C16/0425 ,  G11C16/12 ,  G11C16/14 ,  G11C16/26 ,  G11C16/3454 ,  G11C16/3459

摘要： An operation scheme for operating stably a semiconductor nonvolatile memory device is provided.When hot-hole injection is conducted in the semiconductor nonvolatile memory device of a split gate structure, the hot-hole injection is verified using a crossing point that does not change with time. Thus, an erased state can be verified without being aware of any time-varying changes.Also, programming or programming/erasure is conducted by repeating pulse voltage or multi-step voltage application to a gate section multiple times.

摘要翻译： 提供一种稳定运行半导体非易失性存储器件的操作方案。 当在分裂栅极结构的半导体非易失性存储器件中进行热空穴注入时，使用不随时间变化的交叉点来验证热孔注入。 因此，可以验证擦除状态，而不知道任何时变变化。 此外，通过将多次脉冲电压或多级电压施加到栅极部分进行编程或编程/擦除。

公开(公告)号：US07212444B2

公开(公告)日：2007-05-01

申请号：US11137518

申请日：2005-05-26

申请人： Digh Hisamoto ,  Kan Yasui ,  Tetsuya Ishimaru ,  Shinichiro Kimura ,  Daisuke Okada

发明人： Digh Hisamoto ,  Kan Yasui ,  Tetsuya Ishimaru ,  Shinichiro Kimura ,  Daisuke Okada

IPC分类号： G11C16/04 ,  G11C16/06

CPC分类号： G11C16/0425 ,  G11C16/12 ,  G11C16/14 ,  G11C16/26 ,  G11C16/3454 ,  G11C16/3459

摘要： An operation scheme for operating stably a semiconductor nonvolatile memory device is provided.When hot-hole injection is conducted in the semiconductor nonvolatile memory device of a split gate structure, the hot-hole injection is verified using a crossing point that does not change with time. Thus, an erased state can be verified without being aware of any time-varying changes.Also, programming or programming/erasure is conducted by repeating pulse voltage or multi-step voltage application to a gate section multiple times.

公开(公告)号：US20050265080A1

公开(公告)日：2005-12-01

申请号：US11137518

申请日：2005-05-26

申请人： Digh Hisamoto ,  Kan Yasui ,  Tetsuya Ishimaru ,  Shinichiro Kimura ,  Daisuke Okada

发明人： Digh Hisamoto ,  Kan Yasui ,  Tetsuya Ishimaru ,  Shinichiro Kimura ,  Daisuke Okada

IPC分类号： G11C11/34 ,  G11C16/04 ,  G11C16/12 ,  G11C16/14 ,  G11C16/26 ,  G11C16/34

CPC分类号： G11C16/0425 ,  G11C16/12 ,  G11C16/14 ,  G11C16/26 ,  G11C16/3454 ,  G11C16/3459

摘要： An operation scheme for operating stably a semiconductor nonvolatile memory device is provided. When hot-hole injection is conducted in the semiconductor nonvolatile memory device of a split gate structure, the hot-hole injection is verified using a crossing point that does not change with time. Thus, an erased state can be verified without being aware of any time-varying changes. Also, programming or programming/erasure is conducted by repeating pulse voltage or multi-step voltage application to a gate section multiple times.

摘要翻译： 提供一种稳定运行半导体非易失性存储器件的操作方案。 当在分裂栅极结构的半导体非易失性存储器件中进行热空穴注入时，使用不随时间变化的交叉点来验证热孔注入。 因此，可以验证擦除状态，而不知道任何时变变化。 此外，通过将多次脉冲电压或多级电压施加到栅极部分进行编程或编程/擦除。

公开(公告)号：US07115943B2

公开(公告)日：2006-10-03

申请号：US11013406

申请日：2004-12-17

申请人： Toshiyuki Mine ,  Natsuki Yokoyama ,  Kan Yasui

发明人： Toshiyuki Mine ,  Natsuki Yokoyama ,  Kan Yasui

IPC分类号： H01L29/792

CPC分类号： H01L21/28282 ,  H01L27/11568 ,  H01L29/792

摘要： A MONOS nonvolatile memory of a split gate structure, wherein writing and erasing are performed by hot electrons and hot holes respectively, is prone to cause electrons not to be erased and to remain in an Si nitride film on a select gate electrode sidewall and that results in the deterioration of rewriting durability. When long time erasing is applied as a measure to solve the problem, drawbacks appear, such as the increase of a circuit area caused by the increase of the erasing current and the deterioration of retention characteristics. In the present invention, an Si nitride film is formed by the reactive plasma sputter deposition method that enables oriented deposition and the Si nitride film on a select gate electrode sidewall is removed at the time when a top Si oxide film is formed.

摘要翻译： 分离栅结构的MONOS非易失性存储器，其中由热电子和热孔分别执行写入和擦除容易导致电子不被擦除并且保留在选择栅极电极侧壁上的氮化硅膜中，并且结果 在改写耐久性的恶化。 当长时间擦除作为解决该问题的措施时，会出现缺点，例如由擦除电流的增加引起的电路面积的增加和保留特性的劣化。 在本发明中，通过能够进行取向沉积的反应等离子体溅射沉积方法形成氮化硅膜，并且在形成顶部Si氧化物膜时，在选择栅电极侧壁上除去Si氮化物膜。

公开(公告)号：US07199022B2

公开(公告)日：2007-04-03

申请号：US10814627

申请日：2004-04-01

申请人： Kan Yasui ,  Toshiyuki Mine ,  Yasushi Goto ,  Natsuki Yokoyama

发明人： Kan Yasui ,  Toshiyuki Mine ,  Yasushi Goto ,  Natsuki Yokoyama

IPC分类号： H01L21/76

CPC分类号： H01L21/76224 ,  Y10S438/907

摘要： In order to achieve an isolation trench formation process according to the present invention in which the structure of a silicon nitride film liner can be easily controlled and to allow both of reduction of the device feature length and reduction in stress occurring in an isolation trench, the silicon nitride film liner is first deposited on the inner wall of the trench formed on a silicon substrate. The upper surface of a first embedded insulator film for filling the inside of the trench is recessed downward so as to expose an upper end portion of the silicon nitride film liner. Next, the exposed portion of the silicon nitride film liner is converted into non-silicon-nitride type insulator film, such as a silicon oxide film. A second embedded insulator film is then deposited on the upper portion of the first embedded insulator film, and the deposited surface is then planarized.

摘要翻译： 为了实现根据本发明的隔离沟槽形成方法，其中可以容易地控制氮化硅膜衬垫的结构并且允许器件特征长度的减小和在隔离沟槽中发生的应力的减小， 氮化硅膜衬垫首先沉积在形成在硅衬底上的沟槽的内壁上。 用于填充沟槽内部的第一嵌入式绝缘体膜的上表面向下凹入以暴露氮化硅膜衬垫的上端部分。 接下来，将氮化硅膜衬垫的露出部分转换成诸如氧化硅膜的非氮化硅型绝缘膜。 然后将第二嵌入式绝缘膜沉积在第一嵌入式绝缘膜的上部上，然后将沉积的表面平坦化。

公开(公告)号：US20050199940A1

公开(公告)日：2005-09-15

申请号：US11013406

申请日：2004-12-17

申请人： Toshiyuki Mine ,  Natsuki Yokoyama ,  Kan Yasui

发明人： Toshiyuki Mine ,  Natsuki Yokoyama ,  Kan Yasui

IPC分类号： H01L21/8247 ,  H01L27/115 ,  H01L29/04 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L21/28282 ,  H01L27/11568 ,  H01L29/792

摘要： A MONOS nonvolatile memory of a split gate structure, wherein writing and erasing are performed by hot electrons and hot holes respectively, is prone to cause electrons not to be erased and to remain in an Si nitride film on a select gate electrode sidewall and that results in the deterioration of rewriting durability. When long time erasing is applied as a measure to solve the problem, drawbacks appear, such as the increase of a circuit area caused by the increase of the erasing current and the deterioration of retention characteristics. In the present invention, an Si nitride film is formed by the reactive plasma sputter deposition method that enables oriented deposition and the Si nitride film on a select gate electrode sidewall is removed at the time when a top Si oxide film is formed.

摘要翻译： 分离栅结构的MONOS非易失性存储器分别由热电子和热孔执行写入和擦除，容易导致电子不被擦除并且保留在选择栅电极侧壁上的氮化硅膜中，并且结果 在改写耐久性的恶化。 当长时间擦除作为解决该问题的措施时，会出现缺点，例如由擦除电流的增加引起的电路面积的增加和保留特性的劣化。 在本发明中，通过能够进行取向沉积的反应等离子体溅射沉积方法形成氮化硅膜，并且在形成顶部Si氧化物膜时，在选择栅电极侧壁上除去Si氮化物膜。

公开(公告)号：US08284527B2

公开(公告)日：2012-10-09

申请号：US12957229

申请日：2010-11-30

申请人： Nobuo Yoshida ,  Masato Shiimoto ,  Kenichi Akita ,  Kan Yasui

发明人： Nobuo Yoshida ,  Masato Shiimoto ,  Kenichi Akita ,  Kan Yasui

IPC分类号： G11B5/39

CPC分类号： H01L43/08 ,  B82Y25/00 ,  G01R33/093 ,  G01R33/098 ,  G11B5/3912 ,  G11B5/398

摘要： A magnetic head, according to one embodiment, includes a sensor film, a sensor cap film provided above the sensor film, a pair of shields including an upper magnetic shield and a lower magnetic shield which serve as electrodes that pass current in a film thickness direction of the sensor film, a track insulating film contacting both sides of the sensor film in the track width direction, a graded domain control film arranged on both sides in the track width direction of the sensor film adjacent the track insulating film, and an element height direction insulating film positioned on an opposite side of the sensor film relative to an air-bearing surface, wherein an edge position of the element height direction insulating film adjacent the sensor film on the air-bearing surface side is substantially the same as an edge position of the sensor cap film in the element height direction.

摘要翻译： 根据一个实施例的磁头包括传感器膜，设置在传感器膜上方的传感器盖膜，包括上磁屏蔽和下磁屏蔽的一对屏蔽件，其用作使电流在膜厚度方向上通过的电极 传感器膜的传感器膜的两侧接触的轨道绝缘膜，布置在邻近轨道绝缘膜的传感器膜的轨道宽度方向两侧的梯度控制膜和元件高度 相对于空气轴承表面定位在传感器膜的相对侧上的方向绝缘膜，其中与空气轴承表面侧相邻的传感器膜的元件高度方向绝缘膜的边缘位置与边缘位置基本相同 传感器盖膜在元件高度方向上。