公开(公告)号：US20130083994A1

公开(公告)日：2013-04-04

申请号：US13632405

申请日：2012-10-01

Applicant: Texas Instruments Incorporated

Inventor： Jing-Fei Ren ,  Manish Goel ,  Branislav Kisacanin

IPC: G06K9/36

CPC classification number: G06T7/0075 ,  G06T7/593 ,  G06T7/97 ,  G06T2207/10021 ,  G06T2207/20021

Abstract: A method for disparity cost computation for a stereoscopic image is provided that includes computing path matching costs for external paths of at least some boundary pixels of a tile of a base image of the stereoscopic image, wherein a boundary pixel is a pixel at a boundary between the tile and a neighboring tile in the base image, storing the path matching costs for the external paths, computing path matching costs for pixels in the tile, wherein the stored path matching costs for the external paths of the boundary pixels are used in computing some of the path matching costs of some of the pixels in the tile, and computing aggregated disparity costs for the pixels in the tile, wherein the path matching costs computed for each pixel are used to compute the aggregated disparity costs for the pixel.

Abstract translation: 提供了一种用于立体图像的视差成本计算的方法，其包括针对立体图像的基本图像的图块的至少一些边界像素的外部路径的计算路径匹配成本，其中边界像素是在 存储基本图像中的瓦片和相邻瓦片，存储外部路径的路径匹配成本，对于瓦片中的像素的计算路径匹配成本，其中，边缘像素的外部路径的存储路径匹配成本用于计算一些 的图块中的一些像素的路径匹配成本，以及计算图块中的像素的聚集的差异成本，其中为每个像素计算的路径匹配成本用于计算像素的聚集的视差成本。

公开(公告)号：US11601139B2

公开(公告)日：2023-03-07

申请号：US16680738

申请日：2019-11-12

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Manish Goel ,  Yuming Zhu

IPC: H03M13/13 ,  G06F11/10 ,  G11C29/52

Abstract: Methods, apparatus, systems and articles of manufacture to determine and apply polarity-based error correction code are disclosed. In some examples, the methods and apparatus create an array by setting a first set of bit locations of a code word to have a first value and setting a second set of bit locations of the code word to have a second value different from the first value. In some examples, when the array satisfies a parity check, the methods and apparatus determine that bit locations having the first value from the array form a polarity-based error correction code.

公开(公告)号：US20200334197A1

公开(公告)日：2020-10-22

申请号：US16920901

申请日：2020-07-06

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Srinivas Lingam ,  Seok-Jun Lee ,  Johann Zipperer ,  Manish Goel

IPC: G06F15/80 ,  G06F9/30 ,  G06F9/32 ,  G06F9/38

Abstract: Methods and apparatus for a low energy accelerator processor architecture with short parallel instruction word. An integrated circuit includes a system bus having a data width N, where N is a positive integer; a central processor unit coupled to the system bus and configured to execute instructions retrieved from a memory coupled to the system bus; and a low energy accelerator processor coupled to the system bus and configured to execute instruction words retrieved from a low energy accelerator code memory, the low energy accelerator processor having a plurality of execution units including a load store unit, a load coefficient unit, a multiply unit, and a butterfly/adder ALU unit, each of the execution units configured to perform operations responsive to op-codes decoded from the retrieved instruction words, wherein the width of the instruction words is equal to the data width N. Additional methods and apparatus are disclosed.

公开(公告)号：US10656914B2

公开(公告)日：2020-05-19

申请号：US16545132

申请日：2019-08-20

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Srinivas Lingam ,  Seok-Jun Lee ,  Manish Goel

IPC: G06F7/523 ,  G06F7/50 ,  G06F7/53

Abstract: Instructions for 32-bit arithmetic support using 16-bit multiply and 32-bit addition without a barrel shifter. Illustrative instructions include operations that include receiving a first 32-bit operand, receiving a second 32-bit operand, shifting the second 32-bit operand right 16 or 15 bits to obtain a shifted second 32-bit operand, and adding the shifted second 32-bit operand and the first 32-bit operand to generate a 32-bit sum.

公开(公告)号：US10523240B2

公开(公告)日：2019-12-31

申请号：US15480062

申请日：2017-04-05

Applicant: Texas Instruments Incorporated

Inventor： Manish Goel ,  Yuming Zhu

IPC: H03M13/13 ,  G06F11/10 ,  G11C29/52

Abstract: Methods, apparatus, systems and articles of manufacture to determine and apply polarity-based error correction code are disclosed. In some examples, the methods and apparatus create an array by setting a first set of bit locations of a code word to have a first value and setting a second set of bit locations of the code word to have a second value different from the first value. In some examples, when the array satisfies a parity check, the methods and apparatus determine that bit locations having the first value from the array form a polarity-based error correction code.

公开(公告)号：US10153025B2

公开(公告)日：2018-12-11

申请号：US15710971

申请日：2017-09-21

Applicant: Texas Instruments Incorporated

Inventor： Jose A. Rodriguez-Latorre ,  Hugh P. McAdams ,  Manish Goel

IPC: G11C11/22 ,  G06F11/10 ,  G11C29/52 ,  H03M13/29 ,  G11C29/04

Abstract: Disclosed embodiments include a memory device having a memory array that includes a first memory cell coupled to a first bit line and a second memory cell coupled to a second bit line and a sense amplifier that includes first and second transistors arranged in a cross-coupled configuration with third and fourth transistors, the first and second transistors being of a first conductivity type and the third and fourth transistors being of a second conductivity type, a first inverter having an input coupled to a first common drain terminal of the first and third transistors and an output coupled to the first bit line, and a second inverter having an input coupled to a second common drain terminal of the second and fourth transistors and an output coupled to the second bit line.

公开(公告)号：US20180018298A1

公开(公告)日：2018-01-18

申请号：US15714212

申请日：2017-09-25

Applicant: TEXAS INSTRUMENTS INCORPORATED ,  TEXAS INSTRUMENTS DEUTSCHLAND GMBH

Inventor： Srinivas Lingam ,  Seok-Jun Lee ,  Johann Zipperer ,  Manish Goel

IPC: G06F15/80 ,  G06F9/30 ,  G06F9/32 ,  G06F9/38

Abstract: Methods and apparatus for a low energy accelerator processor architecture with short parallel instruction word. An integrated circuit includes a system bus having a data width N, where N is a positive integer; a central processor unit coupled to the system bus and configured to execute instructions retrieved from a memory coupled to the system bus; and a low energy accelerator processor coupled to the system bus and configured to execute instruction words retrieved from a low energy accelerator code memory, the low energy accelerator processor having a plurality of execution units including a load store unit, a load coefficient unit, a multiply unit, and a butterfly/adder ALU unit, each of the execution units configured to perform operations responsive to op-codes decoded from the retrieved instruction words, wherein the width of the instruction words is equal to the data width N. Additional methods and apparatus are disclosed.

公开(公告)号：US09760301B2

公开(公告)日：2017-09-12

申请号：US14826183

申请日：2015-08-13

Applicant: Texas Instruments Incorporated

Inventor： Yuming Zhu ,  Manish Goel ,  Clive Bittlestone

IPC: G06F12/00 ,  G11C17/00 ,  G06F3/06 ,  G11C17/14 ,  G06F9/445 ,  G06F12/02 ,  G06F17/30

CPC classification number: G06F3/0634 ,  G06F3/0614 ,  G06F3/0616 ,  G06F3/0685 ,  G06F8/66 ,  G06F12/0246 ,  G06F17/30188 ,  G06F2206/1014 ,  G11C17/146

Abstract: A system for write-once memory (WOM) code emulation of EEPROM-type devices includes, for example, a host processor for sending data words for storing in a WOM (Write-Only Memory) device. A host interface receives the data words for encoding by a WOM controller. An emulator programs the WOM-encoded data and an address identifier as an entry of the WOM device. The emulator overwrites previously programmed WOM-encoded data by searching entries of a current active page of a WOM device to locate a programmed WOM entry that includes the searched-for address identifier and the previously written WOM-encoded data word. When the previously written WOM-encoded word cannot be correctly overwritten, the contents of the second WOM-encoded word are stored in a new entry. When the current active page is substantially full, the new entry is stored a new page and the current active page is block-erased.

公开(公告)号：US20170192751A1

公开(公告)日：2017-07-06

申请号：US14986349

申请日：2015-12-31

Applicant: Texas Instruments Incorporated

Inventor： Srinivas Lingam ,  Seok-Jun Lee ,  Manish Goel

IPC: G06F7/523 ,  G06F7/50

CPC classification number: G06F7/523 ,  G06F7/50 ,  G06F7/5324

Abstract: Instructions for 32-bit arithmetic support using 16-bit multiply and 32-bit addition without a barrel shifter. Illustrative instructions include operations that include receiving a first 32-bit operand, receiving a second 32-bit operand, shifting the second 32-bit operand right 16 or 15 bits to obtain a shifted second 32-bit operand, and adding the shifted second 32-bit operand and the first 32-bit operand to generate a 32-bit sum.

公开(公告)号：US20170126414A1

公开(公告)日：2017-05-04

申请号：US14925662

申请日：2015-10-28

Applicant: Texas Instruments Incorporated

Inventor： Manish Goel ,  Joyce Kwong

IPC: H04L9/32 ,  G06F3/06 ,  G06F12/14 ,  H04L9/08

CPC classification number: H04L9/3278 ,  G06F3/0622 ,  G06F3/065 ,  G06F3/0655 ,  G06F3/0679 ,  G06F12/1408 ,  G06F2212/1052 ,  G09C1/00 ,  H04L9/0866 ,  H04L9/3242 ,  H04L2209/12

Abstract: Methods and a device for providing for authentication of an integrated circuit (IC) chip are shown. The IC chip contains a physically unclonable function (PUF), a processor, a non-volatile memory, and an encryption module containing first instructions that, when executed by the processor, receive the unique key from the PUF, receive a master key from an external source, encrypt the unique key using the master key and store the encrypted unique key in the non-volatile memory.