公开(公告)号：US20130181299A1

公开(公告)日：2013-07-18

申请号：US13349942

申请日：2012-01-13

申请人： Tim Baldauf ,  Andy Wei ,  Tom Herrmann ,  Stefan Flachowsky ,  Ralf Illgen

发明人： Tim Baldauf ,  Andy Wei ,  Tom Herrmann ,  Stefan Flachowsky ,  Ralf Illgen

IPC分类号： H01L27/088 ,  H01L21/336

CPC分类号： H01L29/66545 ,  H01L29/66795 ,  H01L29/7846 ,  H01L29/785

摘要： In a three-dimensional transistor configuration, a strain-inducing isolation material is provided, at least in the drain and source areas, thereby inducing a strain, in particular at and in the vicinity of the PN junctions of the three-dimensional transistor. In this case, superior transistor performance may be achieved, while in some illustrative embodiments even the same type of internally stressed isolation material may result in superior transistor performance of P-channel transistors and N-channel transistors.

摘要翻译： 在三维晶体管配置中，至少在漏极和源极区域中提供应变诱导隔离材料，从而引起应变，特别是在三维晶体管的PN结处和附近。 在这种情况下，可以实现卓越的晶体管性能，而在一些说明性实施例中，甚至相同类型的内部应力隔离材料也可能导致P沟道晶体管和N沟道晶体管的优异的晶体管性能。

公开(公告)号：US08349694B2

公开(公告)日：2013-01-08

申请号：US12909149

申请日：2010-10-21

申请人： Stephan Kronholz ,  Markus Lenski ,  Andy Wei ,  Martin Gerhardt

发明人： Stephan Kronholz ,  Markus Lenski ,  Andy Wei ,  Martin Gerhardt

IPC分类号： H01L21/28 ,  H01L27/12 ,  H01L21/8238 ,  H01L21/84 ,  H01L29/165 ,  H01L29/66 ,  H01L29/78

CPC分类号： H01L21/28123 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823871 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7848

摘要： When forming the strain-inducing semiconductor alloy in one type of transistor of a sophisticated semiconductor device, superior thickness uniformity of a dielectric cap material of the gate electrode structures may be achieved by forming encapsulating spacer elements on each gate electrode structure and providing an additional hard mask material. Consequently, in particular, in sophisticated replacement gate approaches, the dielectric cap material may be efficiently removed in a later manufacturing stage, thereby avoiding any irregularities upon replacing the semiconductor material by an electrode metal.

摘要翻译： 当在复杂的半导体器件的一种类型的晶体管中形成应变诱导半导体合金时，可以通过在每个栅极电极结构上形成封装间隔元件并提供额外的硬度来实现栅电极结构的电介质盖材料的优良厚度均匀性 面具材料。 因此，特别地，在复杂的替代栅极方法中，可以在稍后的制造阶段中有效地去除电介质盖材料，从而避免在用电极金属替换半导体材料时的任何不规则性。

公开(公告)号：US08338306B2

公开(公告)日：2012-12-25

申请号：US12886765

申请日：2010-09-21

申请人： Jens Heinrich ,  Ralf Richter ,  Katja Steffen ,  Johannes Groschopf ,  Frank Seliger ,  Andreas Ott ,  Manfred Heinz ,  Andy Wei

发明人： Jens Heinrich ,  Ralf Richter ,  Katja Steffen ,  Johannes Groschopf ,  Frank Seliger ,  Andreas Ott ,  Manfred Heinz ,  Andy Wei

IPC分类号： H01L21/302 ,  H01L21/461

CPC分类号： H01L27/0629

摘要： In a replacement gate approach, the polysilicon material may be efficiently removed during a wet chemical etch process, while the semiconductor material in the resistive structures may be substantially preserved. For this purpose, a species such as xenon may be incorporated into the semiconductor material of the resistive structure, thereby imparting a significantly increased etch resistivity to the semiconductor material. The xenon may be incorporated at any appropriate manufacturing stage.

摘要翻译： 在替代栅极方法中，可以在湿化学蚀刻工艺期间有效地去除多晶硅材料，同时电阻结构中的半导体材料可以被基本保持。 为此，可以将诸如氙的物质并入电阻结构的半导体材料中，从而赋予半导体材料显着增加的蚀刻电阻率。 氙气可以在任何适当的生产阶段进行。

公开(公告)号：US20120211808A1

公开(公告)日：2012-08-23

申请号：US13372837

申请日：2012-02-14

申请人： Andy Wei ,  Peter Baars ,  Richard Carter ,  Frank Ludwig

发明人： Andy Wei ,  Peter Baars ,  Richard Carter ,  Frank Ludwig

IPC分类号： H01L21/336 ,  H01L29/78

CPC分类号： H01L21/823807 ,  H01L21/823412 ,  H01L21/823425 ,  H01L21/823431 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/845 ,  H01L29/1045 ,  H01L29/165 ,  H01L29/41783 ,  H01L29/665 ,  H01L29/66537 ,  H01L29/66545 ,  H01L29/66575 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/78 ,  H01L29/7848

摘要： When forming sophisticated semiconductor devices, three-dimensional transistors in combination with planar transistors may be formed on the basis of a replacement gate approach and self-aligned contact elements by forming the semiconductor fins in an early manufacturing stage, i.e., upon forming shallow trench isolations, wherein the final electrically effective height of the semiconductor fins may be adjusted after the provision of self-aligned contact elements and during the replacement gate approach.

摘要翻译： 当形成复杂的半导体器件时，与平面晶体管组合的三维晶体管可以通过在早期制造阶段中形成半导体翅片（即，在形成浅沟槽隔离时）基于替代栅极接近和自对准接触元件而形成 其中半导体翅片的最终电有效高度可以在提供自对准接触元件之后和在更换栅极接近期间被调整。

公开(公告)号：US08183101B2

公开(公告)日：2012-05-22

申请号：US12620265

申请日：2009-11-17

申请人： Robert Mulfinger ,  Andy Wei ,  Jan Hoentschel ,  Andrew Waite

发明人： Robert Mulfinger ,  Andy Wei ,  Jan Hoentschel ,  Andrew Waite

IPC分类号： H01L29/78

CPC分类号： H01L29/66795 ,  H01L29/785

摘要： The drain and source regions of a multiple gate transistor may be formed without an epitaxial growth process by using a placeholder structure for forming the drain and source dopant profiles and subsequently masking the drain and source areas and removing the placeholder structures so as to expose the channel area of the transistor. Thereafter, corresponding fins may be patterned and a gate electrode structure may be formed. Consequently, reduced cycle times may be accomplished due to the avoidance of the epitaxial growth process.

摘要翻译： 多栅极晶体管的漏极和源极区可以通过使用用于形成漏极和源极掺杂物分布的占位符结构而形成，而不需要外延生长工艺，随后掩蔽漏极和源极区域并去除占位符结构以露出​​沟道 晶体管的面积。 此后，可以对相应的翅片进行构图，并且可以形成栅电极结构。 因此，由于避免了外延生长过程，可以实现缩短的循环时间。

公开(公告)号：US20110241124A1

公开(公告)日：2011-10-06

申请号：US12941185

申请日：2010-11-08

申请人： Andreas Kurz ,  Andy Wei ,  Christoph Schwan

发明人： Andreas Kurz ,  Andy Wei ,  Christoph Schwan

IPC分类号： H01L23/525 ,  H01L21/768

CPC分类号： H01L23/5256 ,  H01L21/28518 ,  H01L27/0629 ,  H01L27/112 ,  H01L27/11206 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： A semiconductor-based electronic fuse may be provided in a sophisticated semiconductor device having a bulk configuration by appropriately embedding the electronic fuse into a semiconductor material of reduced heat conductivity. For example, a silicon/germanium fuse region may be provided in the silicon base material. Consequently, sophisticated gate electrode structures may be formed on the basis of replacement gate approaches on bulk devices substantially without affecting the electronic characteristics of the electronic fuses.

摘要翻译： 可以通过将电子熔丝适当地嵌入到具有降低的导热性的半导体材料中，在具有大体积配置的复杂半导体器件中提供半导体基电子熔断器。 例如，可以在硅基材中提供硅/锗熔丝区域。 因此，可以在大容量装置上的替代栅极接近的基础上形成复杂的栅极电极结构，而不影响电子熔断器的电子特性。

公开(公告)号：US20100301416A1

公开(公告)日：2010-12-02

申请号：US12784819

申请日：2010-05-21

申请人： Jan Hoentschel ,  Stefan Flachowsky ,  Andy Wei

发明人： Jan Hoentschel ,  Stefan Flachowsky ,  Andy Wei

IPC分类号： H01L27/12 ,  H01L21/782

CPC分类号： H01L27/1203 ,  H01L21/823807 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7842 ,  H01L29/7846

摘要： In advanced SOI devices, a high tensile strain component may be achieved on the basis of a globally strained semiconductor layer, while at the same time a certain compressive strain may be induced in P-channel transistors by appropriately selecting a height-to-length aspect ratio of the corresponding active regions. It has been recognized that the finally obtained strain distribution in the active regions is strongly dependent on the aspect ratio of the active regions. Thus, by selecting a moderately low height-to-length aspect ratio for N-channel transistors, a significant fraction of the initial tensile strain component may be preserved. On the other hand, a moderately high height-to-length aspect ratio for the P-channel transistor may result in a compressive strain component in a central surface region of the active region.

摘要翻译： 在先进的SOI器件中，可以在全局应变半导体层的基础上实现高拉伸应变分量，同时通过适当地选择高度 - 长度方面，可以在P沟道晶体管中产生一定的压缩应变 相应活性区的比例。 已经认识到，有效区域中最终获得的应变分布强烈地取决于有源区的纵横比。 因此，通过为N沟道晶体管选择中等的高度 - 长度长宽比，可以保留初始拉伸应变分量的很大一部分。 另一方面，用于P沟道晶体管的中等高度的长宽比可能导致有源区的中心表面区域中的压缩应变分量。

公开(公告)号：US07790537B2

公开(公告)日：2010-09-07

申请号：US11937677

申请日：2007-11-09

申请人： Andy Wei ,  Anthony Mowry ,  Andreas Gehring ,  Maciej Wiatr

发明人： Andy Wei ,  Anthony Mowry ,  Andreas Gehring ,  Maciej Wiatr

IPC分类号： H01L21/336

CPC分类号： H01L29/7842 ,  H01L21/823807 ,  H01L21/823814 ,  H01L27/092 ,  H01L29/6656 ,  H01L29/7843

摘要： By introducing additional strain-inducing mechanisms on the basis of stress memorization techniques, the performance of NMOS transistors may be significantly increased, thereby reducing the imbalance between PMOS transistors and NMOS transistors. By amorphizing and re-crystallizing the respective material in the presence of a mask layer at various stages of the manufacturing process, a drive current improvement of up to approximately 27% has been observed, with the potential for further performance gain.

摘要翻译： 通过在应力记忆技术的基础上引入额外的应变诱导机制，可以显着增加NMOS晶体管的性能，从而减少PMOS晶体管和NMOS晶体管之间的不平衡。 通过在制造过程的不同阶段在掩模层的存在下使各种材料非晶化并再结晶，已经观察到高达约27％的驱动电流改善，具有进一步性能增益的潜力。

公开(公告)号：US07723174B2

公开(公告)日：2010-05-25

申请号：US12464161

申请日：2009-05-12

申请人： Andrew Waite ,  Andy Wei ,  Gunter Grasshoff

发明人： Andrew Waite ,  Andy Wei ,  Gunter Grasshoff

IPC分类号： H01L21/76 ,  H01L21/336

CPC分类号： H01L21/823807 ,  H01L21/823814 ,  H01L21/823835 ,  H01L21/823842 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/7843 ,  H01L29/7848

摘要： The present disclosure relates to semiconductor devices and a process sequence in which a semiconductor alloy, such as silicon/germanium, may be formed in an early manufacturing stage, wherein other performance-increasing mechanisms, such as a recessed drain and source configuration, possibly in combination with high-k dielectrics and metal gates, may be incorporated in an efficient manner while still maintaining a high degree of compatibility with conventional process techniques.

摘要翻译： 本公开涉及半导体器件和其中可以在早期制造阶段中形成诸如硅/锗的半导体合金的工艺顺序，其中其它性能增加机制，例如凹陷漏极和源极配置，可能在 与高k电介质和金属栅极的组合可以以有效的方式并入，同时仍然保持与常规工艺技术的高度兼容性。

公开(公告)号：US07659213B2

公开(公告)日：2010-02-09

申请号：US11566840

申请日：2006-12-05

申请人： Andy Wei ,  Thorsten Kammler ,  Jan Hoentschel ,  Manfred Horstmann

发明人： Andy Wei ,  Thorsten Kammler ,  Jan Hoentschel ,  Manfred Horstmann

IPC分类号： H01L21/31 ,  H01L21/42 ,  H01L21/8222

CPC分类号： C23C8/20 ,  C23C8/80 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7843 ,  H01L29/7848

摘要： By incorporating carbon by means of ion implantation and a subsequent flash-based or laser-based anneal process, strained silicon/carbon material with tensile strain may be positioned in close proximity to the channel region, thereby enhancing the strain-inducing mechanism. The carbon implantation may be preceded by a pre-amorphization implantation, for instance on the basis of silicon. Moreover, by removing a spacer structure used for forming deep drain and source regions, the degree of lateral offset of the strained silicon/carbon material with respect to the gate electrode may be determined substantially independently from other process requirements. Moreover, an additional sidewall spacer used for forming metal silicide regions may be provided with reduced permittivity, thereby additionally contributing to an overall performance enhancement.

摘要翻译： 通过离子注入和随后的基于闪光或基于激光的退火工艺引入碳，具有拉伸应变的应变硅/碳材料可以紧邻通道区域定位，从而增强应变诱导机制。 可以在碳注入之前进行预非晶化注入，例如基于硅。 此外，通过去除用于形成深漏极和源极区的间隔结构，应变硅/碳材料相对于栅极的横向偏移程度可以基本上独立于其它工艺要求来确定。 此外，用于形成金属硅化物区域的附加侧壁间隔物可以具有降低的介电常数，从而另外有助于整体性能提高。