公开(公告)号：US06737739B2

公开(公告)日：2004-05-18

申请号：US10283922

申请日：2002-10-30

Applicant: Shyue-Fong Quek ,  Ting Cheong Ang ,  Duay Ing Ong ,  Sang Yee Loong

Inventor： Shyue-Fong Quek ,  Ting Cheong Ang ,  Duay Ing Ong ,  Sang Yee Loong

IPC: H01L2352

CPC classification number: H01L23/3107 ,  H01L23/5221 ,  H01L23/5222 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/73265 ,  H01L2924/1433 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A semiconductor chip device package comprised of a semiconductor substrate having semiconductor devices formed on the semiconductor substrate. At least one dielectric layer is over the semiconductor substrate. At least one layer of interconnects is over the semiconductor devices and within the at least one respective dielectric layer with at least a portion of the interconnects being separated by voids having a vacuum or air therein. A passivation layer is over the uppermost of the at least one layer of interconnects. Wherein the semiconductor chip device is vacuum sealed within a semiconductor chip device package.

Abstract translation: 一种半导体芯片器件封装，包括形成在半导体衬底上的具有半导体器件的半导体衬底。 至少一个电介质层在半导体衬底之上。 至少一层互连在半导体器件之上，并且在至少一个相应的电介质层内，其中至少一部分互连由其中具有真空或空气的空隙分开。 钝化层位于至少一层互连层的最上面。 其中半导体芯片器件被真空密封在半导体芯片器件封装内。

公开(公告)号：US06486515B2

公开(公告)日：2002-11-26

申请号：US10131536

申请日：2002-04-24

Applicant: Song Jun ,  Ting Cheong Ang ,  Sang Yee Loong ,  Shyue Fong Quek

Inventor： Song Jun ,  Ting Cheong Ang ,  Sang Yee Loong ,  Shyue Fong Quek

IPC: H01L2362

CPC classification number: H01L27/0251 ,  H01L27/1203 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for forming an electrostatic discharge device using silicon-on-insulator technology is described. An N-well is formed within a silicon semiconductor substrate. A P+ region is implanted within a portion of the N-well and an N+ region is implanted within a portion of the semiconductor substrate not occupied by the N-well. An oxide layer is formed overlying the semiconductor substrate and patterned to form openings to the semiconductor substrate. An epitaxial silicon layer is grown within the openings and overlying the oxide layer. Shallow trench isolation regions are formed within the epitaxial silicon layer extending to the underlying oxide layer. Gate electrodes and associated source and drain regions are formed in and on the epitaxial silicon layer between the shallow trench isolation regions. An interlevel dielectric layer is deposited overlying the gate electrodes. First contacts are opened through the interlevel dielectric layer to the underlying source and drain regions. The interlevel dielectric layer is covered with a mask that covers the first contact openings. Second contact openings are opened through the interlevel dielectric layer, shallow trench isolations, and the oxide layer to the N+ region and P+ region. The mask is removed. The first and second contact openings are filled with a conducting layer to complete formation of an ESD device.

Abstract translation: 描述了使用绝缘体上硅技术形成静电放电装置的方法。 在硅半导体衬底内形成N阱。 将P +区注入到N阱的一部分内，并且将N +区注入到不被N阱占据的半导体衬底的一部分内。 在半导体衬底上形成氧化物层并图案化以形成到半导体衬底的开口。 外延硅层生长在开口内并覆盖氧化物层。 在延伸到下面的氧化物层的外延硅层内形成浅沟槽隔离区。 在浅沟槽隔离区域之间的外延硅层中和栅极电极和相关的源极和漏极区域上形成栅电极。 沉积覆盖栅电极的层间电介质层。 第一触点通过层间介质层开放到下面的源极和漏极区域。 用覆盖第一接触开口的掩模覆盖层间电介质层。 第二接触开口通过层间介质层，浅沟槽隔离层和氧化物层开放到N +区域和P +区域。 去除面具。 第一和第二接触开口填充有导电层以完成ESD装置的形成。

公开(公告)号：US06399431B1

公开(公告)日：2002-06-04

申请号：US09531786

申请日：2000-03-21

Applicant: Jun Song ,  Ting Cheong Ang ,  Shyue Fong Quek ,  Sang Yee Loong

Inventor： Jun Song ,  Ting Cheong Ang ,  Shyue Fong Quek ,  Sang Yee Loong

IPC: H01L2170

CPC classification number: H01L21/84 ,  H01L27/0266 ,  H01L27/1203 ,  H01L29/78603

Abstract: A method for forming an electrostatic discharge device using silicon-on-insulator technology is described. A silicon-on-insulator substrate is provided comprising a semiconductor substrate underlying an oxide layer underlying a silicon layer. The silicon layer and oxide layer are patterned to form a gate electrode wherein the semiconductor substrate is exposed. Ions are implanted into the exposed semiconductor substrate to form source and drain regions adjacent to the gate electrode. Spacers are formed on sidewalls of the gate electrode. An interlevel dielectric layer is deposited overlying the gate electrode. Openings are formed through the interlevel dielectric layer to the source and drain regions and filled with a conducting layer. The conducting layer is patterned to form conducting lines to complete formation of an electrostatic discharge device using SOI technology in the fabrication of integrated circuits.

Abstract translation: 描述了使用绝缘体上硅技术形成静电放电装置的方法。 提供了一种绝缘体上硅衬底，其包括位于硅层下面的氧化物层下方的半导体衬底。 图案化硅层和氧化物层以形成其中暴露半导体衬底的栅电极。 将离子注入到暴露的半导体衬底中以形成与栅电极相邻的源区和漏区。 隔板形成在栅电极的侧壁上。 沉积在栅电极上的层间电介质层。 开口通过层间介电层形成到源区和漏区，并填充有导电层。 图案化导电层以形成导线，以在集成电路的制造中使用SOI技术完成静电放电装置的形成。

公开(公告)号：US06376379B1

公开(公告)日：2002-04-23

申请号：US09495344

申请日：2000-02-01

Applicant: Shyue Fong Quek ,  Ting Cheong Ang ,  Jun Song ,  Sang Yee Loong

Inventor： Shyue Fong Quek ,  Ting Cheong Ang ,  Jun Song ,  Sang Yee Loong

IPC: H01L21302

CPC classification number: H01L21/31144 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/32139 ,  H01L21/76801 ,  H01L21/76807 ,  H01L21/76829

Abstract: A method of patterning a hard mask, the comprising the following steps. A semiconductor structure is provided. A conductor film is formed over the semiconductor structure. An oxide layer is formed over the conductor film. A patterned metal oxide layer is formed over the conductor film. The oxide layer and the conductor film are etched, using the metal oxide layer as a hard mask, to form a patterned structure.

Abstract translation: 图案化硬掩模的方法，包括以下步骤。 提供半导体结构。 在半导体结构上形成导体膜。 在导体膜上形成氧化物层。 在导体膜上形成图案化的金属氧化物层。 使用金属氧化物层作为硬掩模来蚀刻氧化物层和导体膜，以形成图案化结构。

公开(公告)号：US06300172B1

公开(公告)日：2001-10-09

申请号：US09409887

申请日：1999-10-01

Applicant: Ting Cheong Ang ,  Shyue Pong Quek ,  Lap Chan ,  Sang Yee Loong

Inventor： Ting Cheong Ang ,  Shyue Pong Quek ,  Lap Chan ,  Sang Yee Loong

IPC: H01L2100

CPC classification number: H01L21/76264 ,  H01L21/76281

Abstract: A method of fabricating an SOI transistor device comprises the following steps. a silicon semiconductor structure is provided. A silicon oxide layer is formed over the silicon semiconductor structure. A silicon-on-insulator layer is formed over the oxide layer. A well is implanted in the silicon-on-insulator layer. A gate oxide layer is grown over the silicon-on-insulator layer. A polysilicon layer is deposited over the gate oxide layer. The polysilicon layer, gate oxide layer, and silicon oxide layer are patterned and etched to form trenches. The trenches are filled with an isolation material to at least a level even with a top surface of the polysilicon layer to form raised shallow trench isolation regions (STIs). The polysilicon layer is patterned and the non-gate portions are removed polysilicon adjacent the raised STIs forming a gate conductor between the raised STIs with the gate conductor and said raised STIs having exposed sidewalls. The gate oxide layer is removed between the gate conductor and the raised STIs, and outboard of the raised STIs. The source and drain are formed in the silicon-on-insulator layer adjacent the gate spacers. Silicide regions may then be formed on the source and drain.

Abstract translation: 制造SOI晶体管器件的方法包括以下步骤。 提供硅半导体结构。 在硅半导体结构上形成氧化硅层。 在氧化物层上形成绝缘体上硅层。 将阱注入绝缘体上硅层中。 栅氧化层生长在绝缘体上硅层上。 在栅极氧化物层上沉积多晶硅层。 对多晶硅层，栅极氧化物层和氧化硅层进行图案化和蚀刻以形成沟槽。 沟槽用隔离材料填充至少甚至具有多晶硅层的顶表面的水平以形成凸起的浅沟槽隔离区域（STI）。 多晶硅层被图案化，并且非栅极部分去除与凸起的STI相邻的多晶硅，其在栅极导体和所述凸起的STI具有暴露的侧壁之间在凸起的STI之间形成栅极导体。 栅极氧化物层在栅极导体和凸起的STI之间以及凸起的STIs的外侧被移除。 源极和漏极形成在邻近栅极间隔物的绝缘体上硅层中。 然后可以在源极和漏极上形成硅化物区域。

公开(公告)号：US06284609B1

公开(公告)日：2001-09-04

申请号：US09435437

申请日：1999-11-22

Applicant: Ting Cheong Ang ,  Shyue Fong Quek ,  Puay Ing Ong ,  Sang Yee Loong

Inventor： Ting Cheong Ang ,  Shyue Fong Quek ,  Puay Ing Ong ,  Sang Yee Loong

IPC: H01L21336

CPC classification number: H01L29/66628 ,  H01L21/2257 ,  H01L21/28026 ,  H01L21/2807 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/7834

Abstract: A new method of fabricating a sub-quarter micron MOSFET device is achieved. A semiconductor substrate is provided. Isolation regions are formed in this substrate. An oxide layer is provided overlying both the substrate and the isolation regions. The oxide layer is patterned and etched exposing two regions of the substrate. A selective epitaxial growth (SEG) is performed with in situ doping covering the two exposed substrate regions formed during the previous step. The doped SEG regions will form the source and drain contact regions of the MOSFET. The oxide layer region between the two doped SEG regions is then patterned and etched away exposing the substrate. This is followed by a gate oxide formation and either a polysilicon or metal gate deposition. Planarization is then performed on the surface to facilitate interconnection later in the process and to form the final gate structure. Thermal energy provided from processing steps or from a rapid thermal anneal (RTA) allows the doping atoms in the SEG regions to diffuse into the substrate thereby forming the active source/drain regions. This method allows precise control of the doping profile in the active source/drain region. An interlevel dielectric is then deposited over the entire surface. Contact holes are then etched in the interlevel dielectric and metalization patterned to allow interconnection to the completed MOSFET device.

Abstract translation: 实现了制造二分之一微米MOSFET器件的新方法。 提供半导体衬底。 在该衬底中形成隔离区。 提供覆盖衬底和隔离区域的氧化物层。 图案化和蚀刻氧化层暴露衬底的两个区域。 通过原位掺杂来执行选择性外延生长（SEG），覆盖在前一步骤期间形成的两个暴露的衬底区域。 掺杂的SEG区域将形成MOSFET的源极和漏极接触区域。 然后将两个掺杂的SEG区域之间的氧化物层区域图案化并蚀刻掉，暴露衬底。 之后是栅极氧化物形成和多晶硅或金属栅极沉积。 然后在表面上执行平面化，以便在该过程中稍后进行互连并形成最终的栅极结构。 从加工步骤或快速热退火（RTA）提供的热能允许SEG区域中的掺杂原子扩散到衬底中，从而形成有源源极/漏极区域。 该方法允许精确控制有源源极/漏极区域中的掺杂分布。 然后在整个表面上沉积层间电介质。 然后在层间电介质中蚀刻接触孔，并图案化金属化，以允许与完成的MOSFET器件互连。

公开(公告)号：US06261917B1

公开(公告)日：2001-07-17

申请号：US09567420

申请日：2000-05-09

Applicant: Shyue Fong Quek ,  Ting Cheong Ang ,  Sang Yee Loong ,  Puay Ing Ong

Inventor： Shyue Fong Quek ,  Ting Cheong Ang ,  Sang Yee Loong ,  Puay Ing Ong

IPC: H01L2120

CPC classification number: H01L28/40 ,  H01L21/31683 ,  H01L28/75

Abstract: A method for fabricating a metal-oxide-metal capacitor is described. A first insulating layer is provided overlying a semiconductor substrate. A barrier metal layer and a first metal layer are deposited over the insulating layer. A titanium layer is deposited overlying the first metal layer. The titanium layer is exposed to an oxidizing plasma while simultaneously a portion of the titanium layer where the metal-oxide-metal capacitor is to be formed is exposed to light whereby the portion of the titanium layer exposed to light reacts with the oxidizing plasma to form titanium oxide. Thereafter, the titanium layer is removed, leaving the titanium oxide layer where the metal-oxide-metal capacitor is to be formed. A second metal layer is deposited overlying the first metal layer and the titanium oxide layer. The second metal layer, titanium oxide layer, and first metal layer are patterned to form a metal-oxide-metal capacitor wherein the second metal layer forms an upper plate electrode, the titanium oxide layer forms a capacitor dielectric, and the first metal layer forms a bottom plate electrode of the MOM capacitor.

Abstract translation: 对金属氧化物 - 金属电容器的制造方法进行说明。 第一绝缘层设置在半导体衬底上。 在绝缘层上沉积阻挡金属层和第一金属层。 沉积钛层沉积在第一金属层上。 将钛层暴露于氧化等离子体，同时将要形成金属 - 氧化物 - 金属电容器的钛层的一部分暴露于光，由此暴露于光的钛层的部分与氧化等离子体反应形成 氧化钛。 然后，除去钛层，留下要形成金属 - 氧化物 - 金属电容器的氧化钛层。 沉积在第一金属层和氧化钛层上的第二金属层。 对第二金属层，氧化钛层和第一金属层进行构图以形成金属氧化物 - 金属电容器，其中第二金属层形成上板电极，氧化钛层形成电容器电介质，第一金属层形成 MOM电容器的底板电极。

公开(公告)号：US06177324B1

公开(公告)日：2001-01-23

申请号：US09428568

申请日：1999-10-28

Applicant: Jun Song ,  Shyue Fong Quek ,  Ting Cheong Ang ,  Lap Chan

Inventor： Jun Song ,  Shyue Fong Quek ,  Ting Cheong Ang ,  Lap Chan

IPC: H01L21336

CPC classification number: H01L29/66621 ,  H01L27/0266 ,  H01L29/0649 ,  H01L29/7834

Abstract: A new method is provided for the creation of an ESD protection device for deep submicron semiconductor technology. An STI trench is created and filled with oxide. The surface of the STI region is polished after which a gate structure is created over the STI region. A high energy ESD implant is performed that is self-aligned with the created gate structure after which the EDS device structure is completed by implanting the source and drain regions of the ESD device.

Abstract translation: 提供了一种用于创建深亚微米半导体技术的ESD保护器件的新方法。 产生STI沟槽并填充氧化物。 抛光STI区域的表面，之后在STI区域上形成栅极结构。 执行高能量ESD注入，其与所产生的栅极结构自对准，之后通过注入ESD器件的源极和漏极区域来完成EDS器件结构。

公开(公告)号：US6110787A

公开(公告)日：2000-08-29

申请号：US391886

申请日：1999-09-07

Applicant: Lap Chan ,  Ting Cheong Ang ,  Shyue Pong Quek ,  Sang Yee Loong

Inventor： Lap Chan ,  Ting Cheong Ang ,  Shyue Pong Quek ,  Sang Yee Loong

IPC: H01L21/336 ,  H01L21/762 ,  H01L29/417 ,  H01L29/423

CPC classification number: H01L29/41775 ,  H01L21/76224 ,  H01L29/41783 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/78

Abstract: A method of fabricating a MOS device having raised source/drain, raised isolation regions having isolation spacers, and a gate conductor having gate spacers is achieved. A layer of gate silicon oxide is grown over the surface of a semiconductor structure. A polysilicon layer is deposited overlying the gate silicon oxide layer. The polysilicon layer, gate silicon oxide layer and semiconductor structure are patterned and etched to form trenches. The trenches are filled with an isolation material to at least a level even with a top surface of the polysilicon layer to form raised isolation regions. The remaining polysilicon layer is patterned to remove polysilicon adjacent the raised isolation regions forming a gate conductor between the raised isolation regions. The gate conductor and the raised isolation regions having exposed sidewalls. The gate oxide layer between the gate conductor and raised isolation regions is removed. Isolation spacers are formed on the exposed sidewalls of the raised isolation regions and gate spacers are formed on the exposed sidewalls of the gate conductor. A layer of silicon is deposited and patterned to form raised source and drain adjacent the gate spacers with source and drain being doped to form a MOS device.

Abstract translation: 实现了具有升高的源极/漏极，具有隔离间隔物的升高的隔离区域以及具有栅极间隔物的栅极导体的MOS器件的制造方法。 在半导体结构的表面上生长栅极氧化硅层。 沉积覆盖栅氧化硅层的多晶硅层。 对多晶硅层，栅极氧化硅层和半导体结构进行图案化和蚀刻以形成沟槽。 沟槽用隔离材料填充至少甚至具有多晶硅层的顶表面的水平以形成凸起的隔离区域。 将剩余的多晶硅层图案化以去除在凸起的隔离区域之间形成栅极导体的凸起的隔离区域附近的多晶硅。 栅极导体和凸起的隔离区域具有暴露的侧壁。 去除栅极导体与升高隔离区之间的栅极氧化层。 在凸起的隔离区域的暴露的侧壁上形成绝缘间隔物，并且栅极间隔物形成在栅极导体的暴露的侧壁上。 沉积一层硅并图案化以形成与栅极间隔物相邻的凸起源极和漏极，源极和漏极被掺杂以形成MOS器件。

公开(公告)号：US20110198734A1

公开(公告)日：2011-08-18

申请号：US13095847

申请日：2011-04-27

Applicant: Ting Cheong Ang

Inventor： Ting Cheong Ang

IPC: H01L29/06

CPC classification number: H01L21/76232

Abstract: A method of forming a graded trench for a shallow trench isolation region is provided. The method includes providing a semiconductor substrate with a substrate region. The method further includes forming a pad oxide layer overlying the substrate region. Additionally, the method includes forming an etch stop layer overlying the pad oxide layer. The method further includes patterning the etch stop layer and the pad oxide layer to expose a portion of the substrate region. In addition, the method includes forming a trench within an exposed portion of the substrate region, the trench having sidewalls and a bottom and a first depth. The method additionally includes forming a dielectric layer overlying the trench sidewalls, the trench bottom, and mesa regions adjacent to the trench. The method further includes removing a first portion of the dielectric layer from the trench bottom to expose the substrate region with a second portion of the dielectric layer remaining on the sidewalls of the trench. In addition, the method includes etching the substrate region to increase the depth of at least a portion of the trench to a second depth. Also, the method includes removing the second portion of the dielectric layer from the trench.

Abstract translation: 提供了形成浅沟槽隔离区域的分级沟槽的方法。 该方法包括提供具有衬底区域的半导体衬底。 该方法还包括形成覆盖衬底区域的衬垫氧化物层。 另外，该方法包括形成覆盖衬垫氧化物层的蚀刻停止层。 该方法还包括图案化蚀刻停止层和衬垫氧化物层以暴露衬底区域的一部分。 此外，该方法包括在衬底区域的暴露部分内形成沟槽，沟槽具有侧壁和底部以及第一深度。 该方法另外包括形成覆盖沟槽侧壁，沟槽底部和与沟槽相邻的台面区域的介电层。 该方法还包括从沟槽底部去除电介质层的第一部分以暴露衬底区域，其中介电层的第二部分保留在沟槽的侧壁上。 此外，该方法包括蚀刻衬底区域以将沟槽的至少一部分的深度增加到第二深度。 此外，该方法包括从沟槽去除电介质层的第二部分。