摘要:
The invention includes a method of implanting dopants into a semiconductor structure wherein a lateral periphery of a photoresist mask is shifted after implanting a first dopant and prior to implanting a second dopant. The invention also includes semiconductor structures having two doped regions of a semiconductive material separated by a region less heavily doped than the doped regions.
摘要:
A process for making a local interconnect and the structures formed thereby. The process is practiced by forming a Ti layer having a nitrogen-rich upper portion over a portion of a substrate, forming a refractory metal layer on the Ti layer, forming a Si layer on the refractory metal layer, removing a portion of the Si layer, and heating to form a local interconnect structure. During this process, a source structure for the local interconnect is formed. This source structure comprises a Ti layer having a nitrogen-rich upper portion overlying a portion of a substrate, a refractory metal layer overlying the Ti layer, and a silicon layer overlying the refractory metal layer. The resulting local interconnect comprises a titanium silicide layer disposed on a portion of a substrate, a nitrogen-rich Ti layer disposed on the titanium silicide layer, and a refractory-metal silicide layer disposed on the nitrogen-rich Ti layer. The local interconnect is especially useful for reducing cratering and consumption of silicon regions underlying the local interconnect.
摘要:
In accordance with an aspect of the invention, a transistor is formed having a transistor gate, a gate dielectric layer and source/drain regions. The transistor gate includes at least two conductive layers of different conductive materials. One of the two conductive layers is more proximate the gate dielectric layer than the other of the two conductive layers. A source/drain reoxidation is conducted prior to forming the other conductive layer. In another aspect of the invention, a transistor has a transistor gate, a gate dielectric layer and source/drain regions. The transistor gate includes a tungsten layer. A source/drain reoxidation is conducted prior to forming the tungsten layer of the gate. In yet another aspect of the invention, a semiconductor processing method forms a transistor gate having insulative sidewall spacers thereover. After forming the insulative sidewall spacers, an outer conductive tungsten layer of the transistor gate is formed.
摘要:
A method of forming capacitorless DRAM over localized silicon-on-insulator comprises the following steps: A silicon substrate is provided, and an array of silicon studs is defined within the silicon substrate. An insulator layer is defined atop at least a portion of the silicon substrate, and between the silicon studs. A silicon-over-insulator layer is defined surrounding the silicon studs atop the insulator layer, and a capacitorless DRAM is formed within and above the silicon-over-insulator layer.
摘要:
Semiconductor memory devices having recessed access devices are disclosed. In some embodiments, a method of forming the recessed access device includes forming a device recess in a substrate material that extends to a first depth in the substrate that includes a gate oxide layer in the recess. The device recess may be extended to a second depth that is greater that the first depth to form an extended portion of the device recess. A field oxide layer may be provided within an interior of the device recess that extends inwardly into the interior of the device recess and into the substrate. Active regions may be formed in the substrate that abut the field oxide layer, and a gate material may be deposited into the device recess.
摘要:
A method of depositing dielectric material into sub-micron spaces and resultant structures is provided. After a trench is etched in the surface of a wafer, an oxygen barrier is deposited into the trench. An expandable, oxidizable liner, preferably amorphous silicon, is then deposited. The trench is then filled with a spin-on dielectric (SOD) material. A densification process is then applied, whereby the SOD material contracts and the oxidizable liner expands. Preferably, the temperature is ramped up while oxidizing during at least part of the densification process. The resulting trench has a negligible vertical wet etch rate gradient and a negligible recess at the top of the trench.
摘要:
A method of forming capacitorless DRAM over localized silicon-on-insulator comprises the following steps: A silicon substrate is provided, and an array of silicon studs is defined within the silicon substrate. An insulator layer is defined atop at least a portion of the silicon substrate, and between the silicon studs. A silicon-over-insulator layer is defined surrounding the silicon studs atop the insulator layer, and a capacitorless DRAM is formed within and above the silicon-over-insulator layer.
摘要:
A method of forming capacitorless DRAM over localized silicon-on-insulator comprises the following steps: A silicon substrate is provided, and an array of silicon studs is defined within the silicon substrate. An insulator layer is defined atop at least a portion of the silicon substrate, and between the silicon studs. A silicon-over-insulator layer is defined surrounding the silicon studs atop the insulator layer, and a capacitorless DRAM is formed within and above the silicon-over-insulator layer.
摘要:
An antifuse including a bottom plate having a plurality of longitudinal members arranged substantially parallel to a first axis, a dielectric layer formed on the bottom plate, and a top plate having a plurality of longitudinal members arranged substantially parallel to a second axis, the top plate formed over the dielectric layer. Multiple edges formed at the interfaces between the top and bottom plates result in regions of localized charge concentration when a programming voltage is applied across the antifuse. As a result, the formation of the antifuse dielectric over the corners of the bottom plates enhance the electric field during programming of the antifuse. Reduced programming voltages can be used in programming the antifuse and the resulting conductive path between the top and bottom plates will likely form along the multiple edges.
摘要:
An improved method of making CMOS surface channel transistors using fewer masking steps. In-situ doped poly silicon deposition can be used to reduce problems with poly depletion effects in transistor gates. In addition, using this method, the number of layers in each gate dielectric, the dielectric type, and dielectric thickness between n-channel and p-channel devices can be separately controlled. This method also allows the use of a lithography mask normally used to fabricate buried channel devices for use in fabricating surface channel devices, thus saving the manufacture of an additional mask.