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公开(公告)号：US20230329006A1
公开(公告)日：2023-10-12
申请号：US18207654
申请日：2023-06-08
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Hui-Lin Wang , Po-Kai Hsu , Jing-Yin Jhang , Yu-Ping Wang , Hung-Yueh Chen , Wei Chen
Abstract: A method for fabricating a semiconductor device includes the steps of: forming a magnetic tunneling junction (MTJ) on a substrate; forming a first inter-metal dielectric (IMD) layer around the MTJ; forming a first metal interconnection adjacent to the MTJ; forming a stop layer on the first IMD layer; removing the stop layer to form an opening; and forming a channel layer in the opening to electrically connect the MTJ and the first metal interconnection.
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公开(公告)号：US11723295B2
公开(公告)日：2023-08-08
申请号：US17551214
申请日：2021-12-15
Applicant: United Microelectronics Corp.
Inventor： Hai Tao Liu , Li Li Ding , Yao-Hung Liu , Guoan Du , Qi Lu Li , Chunlei Wan , Yi Yu Lin , Yuchao Chen , Huakai Li , Hung-Yueh Chen
CPC classification number: H10N70/8833 , H10B63/80 , H10N70/028 , H10N70/24 , H10N70/826 , H10N70/8265 , H10N70/841
Abstract: A method for fabricating memory device includes: providing a substrate having a bottom electrode layer therein, forming a buffer layer and a mask layer on the buffer layer over the substrate, in contact with the bottom electrode layer, performing an advanced oxidation process on a sidewall of the buffer layer to form a resistive layer, which surrounds the whole sidewall of the buffer layer and extends upward vertically from the substrate, and forming, over the substrate, a noble metal layer and a top electrode layer on the noble metal layer, fully covering the resistive layer and the mask layer.
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公开(公告)号：US11716860B2
公开(公告)日：2023-08-01
申请号：US16882783
申请日：2020-05-26
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Hui-Lin Wang , Po-Kai Hsu , Jing-Yin Jhang , Yu-Ping Wang , Hung-Yueh Chen , Wei Chen
Abstract: A method for fabricating a semiconductor device includes the steps of: forming a magnetic tunneling junction (MTJ) on a substrate; forming a first inter-metal dielectric (IMD) layer around the MTJ; forming a first metal interconnection adjacent to the MTJ; forming a stop layer on the first IMD layer; removing the stop layer to form an opening; and forming a channel layer in the opening to electrically connect the MTJ and the first metal interconnection.
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公开(公告)号：US11616193B2
公开(公告)日：2023-03-28
申请号：US17338632
申请日：2021-06-03
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Hui-Lin Wang , Po-Kai Hsu , Chen-Yi Weng , Jing-Yin Jhang , Yu-Ping Wang , Hung-Yueh Chen
Abstract: A semiconductor device includes: a substrate comprising a magnetic tunneling junction (MTJ) region and a logic region, a MTJ on the MTJ region, a top electrode on the MTJ, a connecting structure on the top electrode, and a first metal interconnection on the logic region. Preferably, the first metal interconnection includes a via conductor on the substrate and a trench conductor, in which a bottom surface of the trench conductor is lower than a bottom surface of the connecting structure.
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35.发明授权公开(公告)号：US11522013B2
公开(公告)日：2022-12-06
申请号：US17033901
申请日：2020-09-27
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Po-Kai Hsu , Hui-Lin Wang , Ching-Hua Hsu , Yi-Yu Lin , Ju-Chun Fan , Hung-Yueh Chen
Abstract: A hybrid random access memory for a system-on-chip (SOC), including a semiconductor substrate with a MRAM region and a ReRAM region, a first dielectric layer on the semiconductor substrate, multiple ReRAM cells in the first dielectric layer on the ReRAM region, a second dielectric layer above the first dielectric layer, and multiple MRAM cells in the second dielectric layer on the MRAM region.
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Patent Agency Ranking
公开(公告)号：US11355700B2
公开(公告)日：2022-06-07
申请号：US16732359
申请日：2020-01-02
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Hui-Lin Wang , Po-Kai Hsu , Hung-Yueh Chen , Yu-Ping Wang
Abstract: A method for fabricating semiconductor device includes the steps of: forming a magnetic tunneling junction (MTJ) stack on a substrate; forming a top electrode on the MTJ stack; performing a first patterning process to remove the MTJ stack for forming a first MTJ; forming a first inter-metal dielectric (IMD) layer around the first MTJ; and performing a second patterning process to remove the first MTJ for forming a second MTJ and a third MTJ.
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公开(公告)号：US20210225933A1
公开(公告)日：2021-07-22
申请号：US16792271
申请日：2020-02-16
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Ya-Huei Tsai , Rai-Min Huang , Yu-Ping Wang , Hung-Yueh Chen
IPC: H01L27/22 , H01L23/528 , H01L43/02
Abstract: A layout pattern for magnetoresistive random access memory (MRAM) includes a substrate having a first active region, a second active region, and a word line connecting region between the first active region and the second active region and a gate pattern extending from the first active region to the second active region, in which the gate pattern includes a H-shape according to a top view. Preferably, the gate pattern includes a first gate pattern extending along a first direction from the first active region to the second active region, a second gate pattern extending along the first direction from the first active region to the second active region, and a third gate pattern connecting the first gate pattern and the second gate pattern along a second direction.
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公开(公告)号：US20210225414A1
公开(公告)日：2021-07-22
申请号：US17224153
申请日：2021-04-07
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Po-Kai Hsu , Hung-Yueh Chen , Kun-I Chou , Jing-Yin Jhang , Hui-Lin Wang , Yu-Ping Wang
Abstract: A MRAM structure, which is provided with multiple source lines between active areas, each source line has multiple branches electrically connecting with the active areas at opposite sides in alternating arrangement. Multiple word lines traverse through the active areas to form transistors. Multiple storage units are disposed between the word lines on the active areas in staggered array arrangement, and multiple bit lines electrically connect with storage units on corresponding active areas, wherein each storage cell includes one of the storage unit, two of the transistors respectively at both sides of the storage unit, and two branches of the source line.
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公开(公告)号：US12063792B2
公开(公告)日：2024-08-13
申请号：US18207654
申请日：2023-06-08
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Hui-Lin Wang , Po-Kai Hsu , Jing-Yin Jhang , Yu-Ping Wang , Hung-Yueh Chen , Wei Chen
Abstract: A method for fabricating a semiconductor device includes the steps of: forming a magnetic tunneling junction (MTJ) on a substrate; forming a first inter-metal dielectric (IMD) layer around the MTJ; forming a first metal interconnection adjacent to the MTJ; forming a stop layer on the first IMD layer; removing the stop layer to form an opening; and forming a channel layer in the opening to electrically connect the MTJ and the first metal interconnection.
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公开(公告)号：US20240196756A1
公开(公告)日：2024-06-13
申请号：US18587823
申请日：2024-02-26
Applicant: United Microelectronics Corp.
Inventor： Hui-Lin Wang , Wei Chen , Po-Kai Hsu , Yu-Ping Wang , Hung-Yueh Chen
CPC classification number: H10N50/01 , H01F10/3254 , H01F10/329 , H10N50/80
Abstract: A method for fabricating a semiconductor device includes the steps of: forming a first inter-metal dielectric (IMD) layer on a substrate; forming a first metal interconnection and a second metal interconnection in the first IMD layer; forming a channel layer on the first metal interconnection and the second metal interconnection; forming a magnetic tunneling junction (MTJ) stack on the channel layer; and removing the MTJ stack to form a MTJ.
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