公开(公告)号：US20240379670A1

公开(公告)日：2024-11-14

申请号：US18206609

申请日：2023-06-06

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ya-Ting Hu ,  Chih-Yi Wang ,  Yao-Jhan Wang ,  Wei-Che Chen ,  Kun-Szu Tseng ,  Yun-Yang He ,  Wen-Liang Huang ,  Lung-En Kuo ,  Po-Tsang Chen ,  Po-Chang Lin ,  Ying-Hsien Chen

IPC: H01L27/088 ,  H01L21/762

Abstract: A semiconductor device includes a substrate with a high voltage region and a low voltage region. A first deep trench isolation is disposed within the high voltage region. The first deep trench isolation includes a first deep trench and a first insulating layer filling the first deep trench. The first deep trench includes a first sidewall and a second sidewall facing the first sidewall. The first sidewall is formed by a first plane and a second plane. The edge of the first plane connects to the edge of the second plane. The slope of the first plane is different from the slope of the second plane.

公开(公告)号：US20240243124A1

公开(公告)日：2024-07-18

申请号：US18110353

申请日：2023-02-15

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Wei Yang ,  Shih-Min Lu ,  Chi-Sheng Tseng ,  Yao-Jhan Wang ,  Chun-Hsien Lin

IPC: H01L27/088 ,  H01L21/8234

CPC classification number: H01L27/088 ,  H01L21/823456

Abstract: A method for fabricating a semiconductor device includes the steps of first forming a first gate structure on a substrate and then forming a first epitaxial layer adjacent to the first gate structure. Preferably, a top surface of the first epitaxial layer includes a first curve, a second curve, and a third curve connecting the first curve and the second curve, in which the first curve and the second curve include curves concave downward while the third curve includes a curve concave upward.

公开(公告)号：US20230352565A1

公开(公告)日：2023-11-02

申请号：US18218599

申请日：2023-07-06

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Te-Chang Hsu ,  Chun-Chia Chen ,  Yao-Jhan Wang ,  Chun-Jen Huang

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/49 ,  H01L21/768 ,  H01L21/28 ,  H01L21/8238

CPC classification number: H01L29/6656 ,  H01L29/66795 ,  H01L29/66545 ,  H01L29/6653 ,  H01L29/7851 ,  H01L29/4983 ,  H01L29/4966 ,  H01L21/76834 ,  H01L29/4958 ,  H01L21/28247 ,  H01L21/76829 ,  H01L21/76832 ,  H01L21/823821 ,  H01L29/7848 ,  H01L29/0847

Abstract: A method for fabricating semiconductor device includes the steps of: forming a gate structure on a substrate; forming a spacer around the gate structure; forming a first contact etch stop layer (CESL) around the spacer; forming a mask layer on the first CESL; removing part of the mask layer; removing part of the first CESL; forming a second CESL on the mask layer and the gate structure; and removing part of the second CESL.

公开(公告)号：US11569235B2

公开(公告)日：2023-01-31

申请号：US17075729

申请日：2020-10-21

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Yi Wang ,  Tien-Shan Hsu ,  Cheng-Pu Chiu ,  Yao-Jhan Wang

IPC: H01L21/308 ,  H01L27/092 ,  H01L29/78 ,  H01L29/06 ,  H01L29/66 ,  H01L21/8238 ,  H01L29/161 ,  H01L29/26

Abstract: A semiconductor device is provided in the disclosure, including a substrate, multiple parallel fins protruding from the substrate and isolated by trenches, and a device insulating layer on the trenches between two fins, wherein the trench is provided with a central first trench and two second trenches at both sides of the first trench, and a depth of the first trench is deeper than a depth of the second trench, and the device insulating layer is provided with a top plane, a first trench and a second trench, and the fins protrude from the top plane, and the bottom surface of the second trench is lower than the bottom surface of the first trench.

公开(公告)号：US20220069102A1

公开(公告)日：2022-03-03

申请号：US17523946

申请日：2021-11-11

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Jie-Ning Yang ,  Wen-Tsung Chang ,  Po-Wen Su ,  Kuan-Ying Lai ,  Bo-Yu Su ,  Chun-Mao Chiou ,  Yao-Jhan Wang

IPC: H01L29/49 ,  H01L29/423 ,  H01L29/66 ,  H01L21/8234 ,  H01L21/768 ,  H01L29/417

Abstract: A gate structure includes a substrate divided into an N-type transistor region and a P-type transistor region. An interlayer dielectric covers the substrate. A first trench is embedded in the interlayer dielectric within the N-type transistor region. A first gate electrode having a bullet-shaped profile is disposed in the first trench. A gate dielectric contacts the first trench. An N-type work function layer is disposed between the gate dielectric layer and the first gate electrode. A second trench is embedded in the interlayer dielectric within the P-type transistor region. A second gate electrode having a first mushroom-shaped profile is disposed in the second trench. The gate dielectric layer contacts the second trench. The N-type work function layer is disposed between the gate dielectric layer and the second gate electrode. A first P-type work function layer is disposed between the gate dielectric layer and the N-type work function layer.

公开(公告)号：US20200235224A1

公开(公告)日：2020-07-23

申请号：US16836872

申请日：2020-03-31

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Te-Chang Hsu ,  Chun-Chia Chen ,  Yao-Jhan Wang

IPC: H01L29/66 ,  H01L21/3105 ,  H01L21/3115 ,  H01L21/02 ,  H01L21/768

Abstract: A semiconductor device includes a gate structure on a substrate, an offset spacer adjacent to the gate structure, a main spacer around the offset spacer, a source/drain region adjacent to two sides of the main spacer, a contact etch stop layer (CESL) adjacent to the main spacer, and an interlayer dielectric (ILD) layer around the CESL. Preferably, a dielectric constant of the offset spacer is higher than a dielectric constant of the main spacer.

公开(公告)号：US10700163B2

公开(公告)日：2020-06-30

申请号：US16194379

申请日：2018-11-18

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Te-Chang Hsu ,  Che-Hsien Lin ,  Cheng-Yeh Huang ,  Chun-Jen Huang ,  Yu-Chih Su ,  Yao-Jhan Wang

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L29/06 ,  H01L29/417 ,  H01L29/66 ,  H01L21/3213 ,  H01L21/311 ,  H01L29/78

Abstract: A manufacturing method of a semiconductor device includes the following steps. A semiconductor substrate with gate structures formed thereon is provided. A source/drain region is formed in the semiconductor substrate and formed between the gate structures. A dielectric layer is formed on the source/drain region and located between the gate structures. An opening penetrating the dielectric layer on the source/drain region is formed. A lower portion of a first conductive structure is formed in the opening. A dielectric spacer is formed on the lower portion and on an inner wall of the opening. An upper portion of the first conductive structure is formed in the opening and on the lower portion. The dielectric spacer surrounds the upper portion of the first conductive structure. The first conductive structure is formed by two steps for forming the dielectric spacer surrounding the upper portion and improving the electrical performance of the semiconductor device.

公开(公告)号：US10608113B1

公开(公告)日：2020-03-31

申请号：US16162356

申请日：2018-10-16

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Cheng-Yeh Huang ,  Te-Chang Hsu ,  Chun-Jen Huang ,  Che-Hsien Lin ,  Yao-Jhan Wang

IPC: H01L21/762 ,  H01L29/66 ,  H01L29/78 ,  H01L29/04 ,  H01L29/10 ,  H01L21/324 ,  H01L29/51 ,  H01L29/49 ,  H01L21/768 ,  H01L29/161

Abstract: A semiconductor structure includes a semiconductor substrate, at least a silicon germanium (SiGe) epitaxial region disposed in the semiconductor substrate, and a contact structure disposed on the SiGe epitaxial region. The contact structure includes a titanium nitride (TiN) barrier layer and a metal layer surrounded by the TiN barrier layer. A crystalline titanium germanosilicide stressor layer is disposed in the SiGe epitaxial region and between the TiN barrier layer and the SiGe epitaxial region.

公开(公告)号：US20190080968A1

公开(公告)日：2019-03-14

申请号：US15700175

申请日：2017-09-10

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Yi Wang ,  Tien-Shan Hsu ,  Yu-Chih Su ,  Chi-Hsuan Cheng ,  Cheng-Pu Chiu ,  Te-Chang Hsu ,  Chin-Yang Hsieh ,  An-Chi Liu ,  Kuan-Lin Chen ,  Yao-Jhan Wang

IPC: H01L21/8234 ,  H01L21/3065 ,  H01L21/02 ,  H01L21/762

Abstract: A method of fabricating fins includes providing a silicon substrate. The silicon substrate is etched to form numerous fin elements. A surface of each of the fin elements is silicon. Etch residues are formed on the fin elements after the silicon substrate is etched. After that, a flush step is performed on the fin elements by flushing the surface of each of the fin elements with fluorocarbons. The etch residues on the fin elements are removed by the flush step. After the flush step, a strip step is performed on the fin elements by treating the surface of each of the fin elements with oxygen plasma.

公开(公告)号：US10211314B1

公开(公告)日：2019-02-19

申请号：US15790043

申请日：2017-10-22

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Te-Chang Hsu ,  Chun-Chia Chen ,  Yao-Jhan Wang

IPC: H01L21/28 ,  H01L29/66 ,  H01L21/3105 ,  H01L21/3115

Abstract: A method for fabricating semiconductor device includes the steps of first forming a gate structure on a substrate, forming a contact etch stop layer (CESL) on the gate structure, forming an interlayer dielectric (ILD) layer around the gate structure, performing a curing process so that an oxygen concentration of the CESL is different from the oxygen concentration of the ILD layer, and then performing a replacement metal gate process (RMG) process to transform the gate structure into a metal gate.