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公开(公告)号：US20080181003A1
公开(公告)日：2008-07-31
申请号：US11657950
申请日：2007-01-25
IPC分类号： G11C16/06
CPC分类号： G11C16/0483 , G11C16/26
摘要： A method of reading sequential pages of flash memory from alternating memory blocks comprises loading data from a first page into a first primary data cache and a second page into a second primary data cache simultaneously, the first and second pages loaded from different blocks of flash memory. Data from the first primary data cache is stored in a first secondary data cache, and data from the second primary data cache is stored in a second secondary data cache. Data is sequentially provided from the first and second secondary data caches by a multiplexer coupled to the first and second data caches.
摘要翻译： 从交替的存储器块读取闪存的顺序页面的方法包括将数据从第一页面加载到第一主数据高速缓存和第二页面中同时加载到第二主数据高速缓存中，从不同的闪存块加载的第一页和第二页 。 来自第一主数据高速缓存的数据被存储在第一辅助数据高速缓存中，并且来自第二主数据高速缓存的数据被存储在第二次数据高速缓存中。 通过耦合到第一和第二数据高速缓存的多路复用器从第一和第二辅助数据高速缓存顺序地提供数据。
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公开(公告)号：US08520436B2
公开(公告)日：2013-08-27
申请号：US13464531
申请日：2012-05-04
申请人： Dzung H. Nguyen , Benjamin Louie , Hagop A. Nazarian , Aaron Yip , Jin-Man Han
发明人： Dzung H. Nguyen , Benjamin Louie , Hagop A. Nazarian , Aaron Yip , Jin-Man Han
IPC分类号： G11C16/04
CPC分类号： G11C16/10
摘要： A target memory cell of a memory device is programmed by applying a programming voltage to a word line that includes the target memory cell, determining whether the target memory cell is programmed, and increasing the programming voltage by a step voltage if it is determined that the target memory cell is not programmed. An initial programming voltage and the step voltage are each selectable after fabrication of the memory device.
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公开(公告)号：US08174892B2
公开(公告)日：2012-05-08
申请号：US13042071
申请日：2011-03-07
IPC分类号： G11C16/06
CPC分类号： G11C16/0483 , G11C16/26
摘要： A method of reading sequential pages of flash memory from alternating memory blocks comprises loading data from a first page into a first primary data cache and a second page into a second primary data cache simultaneously, the first and second pages loaded from different blocks of flash memory. Data from the first primary data cache is stored in a first secondary data cache, and data from the second primary data cache is stored in a second secondary data cache. Data is sequentially provided from the first and second secondary data caches by a multiplexer coupled to the first and second data caches.
摘要翻译： 从交替的存储器块读取闪存的顺序页面的方法包括将数据从第一页面加载到第一主数据高速缓存和第二页面中同时加载到第二主数据高速缓存中，从不同的闪存块加载的第一页和第二页 。 来自第一主数据高速缓存的数据被存储在第一辅助数据高速缓存中，并且来自第二主数据高速缓存的数据被存储在第二次数据高速缓存中。 通过耦合到第一和第二数据高速缓存的多路复用器从第一和第二辅助数据高速缓存顺序地提供数据。
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公开(公告)号：US20110170353A1
公开(公告)日：2011-07-14
申请号：US12686721
申请日：2010-01-13
申请人： Dzung H. Nguyen
发明人： Dzung H. Nguyen
CPC分类号： G11C16/04 , G11C8/08 , G11C8/14 , G11C16/0483 , G11C16/08
摘要： The present disclosure includes methods, devices, and systems for access line biasing. One embodiment includes selecting, using a controller external to the memory device, a particular access line dependent biasing scheme and corresponding bias conditions for use in performing an access operation on an array of memory cells of the memory device, and performing the access operation using the selected particular access line dependent biasing scheme and corresponding bias conditions. In one or more embodiments, the selected particular access line dependent biasing scheme and corresponding bias conditions is selected by the controller external to the memory device based, at least partially, on a target access line of the array.
摘要翻译： 本公开包括用于接入线偏置的方法，设备和系统。 一个实施例包括：使用存储器设备外部的控制器选择特定的访问线路依赖偏置方案和相应的偏置条件，以用于对存储器件的存储器单元阵列执行访问操作，以及使用 所选择的特定接入线相关偏置方案和相应的偏置条件。 在一个或多个实施例中，所选择的特定访问线路依赖偏置方案和对应的偏置条件由存储器设备外部的至少部分地基于阵列的目标访问线路选择。
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公开(公告)号：US20110161591A1
公开(公告)日：2011-06-30
申请号：US13042071
申请日：2011-03-07
IPC分类号： G06F12/08
CPC分类号： G11C16/0483 , G11C16/26
摘要： A method of reading sequential pages of flash memory from alternating memory blocks comprises loading data from a first page into a first primary data cache and a second page into a second primary data cache simultaneously, the first and second pages loaded from different blocks of flash memory. Data from the first primary data cache is stored in a first secondary data cache, and data from the second primary data cache is stored in a second secondary data cache. Data is sequentially provided from the first and second secondary data caches by a multiplexer coupled to the first and second data caches.
摘要翻译： 从交替的存储器块读取闪存的顺序页面的方法包括将数据从第一页面加载到第一主数据高速缓存和第二页面中同时加载到第二主数据高速缓存中，从不同的闪存块加载的第一页和第二页 。 来自第一主数据高速缓存的数据被存储在第一辅助数据高速缓存中，并且来自第二主数据高速缓存的数据被存储在第二次数据高速缓存中。 通过耦合到第一和第二数据高速缓存的多路复用器从第一和第二辅助数据高速缓存顺序地提供数据。
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公开(公告)号：US20090201736A1
公开(公告)日：2009-08-13
申请号：US12425200
申请日：2009-04-16
CPC分类号： G11C16/0483 , G11C16/26
摘要： A method of reading sequential pages of flash memory from alternating memory blocks comprises loading data from a first page into a first primary data cache and a second page into a second primary data cache simultaneously, the first and second pages loaded from different blocks of flash memory. Data from the first primary data cache is stored in a first secondary data cache, and data from the second primary data cache is stored in a second secondary data cache. Data is sequentially provided from the first and second secondary data caches by a multiplexer coupled to the first and second data caches.
摘要翻译： 从交替的存储器块读取闪存的顺序页面的方法包括将数据从第一页面加载到第一主数据高速缓存和第二页面中同时加载到第二主数据高速缓存中，从不同的闪存块加载的第一页和第二页 。 来自第一主数据高速缓存的数据被存储在第一辅助数据高速缓存中，并且来自第二主数据高速缓存的数据被存储在第二次数据高速缓存中。 通过耦合到第一和第二数据高速缓存的多路复用器从第一和第二辅助数据高速缓存顺序地提供数据。
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公开(公告)号：US07505323B2
公开(公告)日：2009-03-17
申请号：US12025815
申请日：2008-02-05
申请人： Dzung H. Nguyen , Benjamin Louie , Hagop A. Nazarian , Aaron Yip , Jin-Man Han
发明人： Dzung H. Nguyen , Benjamin Louie , Hagop A. Nazarian , Aaron Yip , Jin-Man Han
IPC分类号： G11C11/34
CPC分类号： G11C16/10
摘要： A target memory cell of a memory device is programmed by applying a programming voltage to a word line that includes the target memory cell, determining whether the target memory cell is programmed, and increasing the programming voltage by a step voltage if it is determined that the target memory cell is not programmed. An initial programming voltage and the step voltage are each selectable after fabrication of the memory device.
摘要翻译： 通过将编程电压施加到包括目标存储器单元的字线，确定目标存储器单元是否被编程来编程存储器件的目标存储器单元，并且如果确定所述编程电压被确定为 目标存储单元未编程。 在制造存储器件之后，可以选择初始编程电压和阶跃电压。
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公开(公告)号：US20080130373A1
公开(公告)日：2008-06-05
申请号：US12025815
申请日：2008-02-05
申请人： Dzung H. Nguyen , Benjamin Louie , Hagop A. Nazarian , Aaron Yip , Jin-Man Han
发明人： Dzung H. Nguyen , Benjamin Louie , Hagop A. Nazarian , Aaron Yip , Jin-Man Han
IPC分类号： G11C16/04
CPC分类号： G11C16/10
摘要： A target memory cell of a memory device is programmed by applying a programming voltage to a word line that includes the target memory cell, determining whether the target memory cell is programmed, and increasing the programming voltage by a step voltage if it is determined that the target memory cell is not programmed. An initial programming voltage and the step voltage are each selectable after fabrication of the memory device.
摘要翻译： 通过将编程电压施加到包括目标存储器单元的字线，确定目标存储器单元是否被编程来编程存储器件的目标存储器单元，并且如果确定所述编程电压被确定为 目标存储单元未编程。 在制造存储器件之后，可以选择初始编程电压和阶跃电压。
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公开(公告)号：US06495315B2
公开(公告)日：2002-12-17
申请号：US09758248
申请日：2001-01-12
IPC分类号： C12Q170
CPC分类号： C12N7/00 , A61K38/164 , A61K39/12 , A61K39/21 , A61K2039/55544 , A61K2039/6037 , C12N2740/16034 , C12N2740/16063
摘要： The infectivity of a population of enveloped viruses which comprise a glycosylphosphatidylinositol-anchored protein in their membrane can be reduced by employing certain toxins such as aerolysin, alpha toxin of Clostridium septicum, or enterolobin. Toxins which bind to glycosylphosphatidylinositol-anchored proteins inactivate such viruses. The toxins can be used to produce attenuated viral vaccines, to purge blood products, cells, or tissues of such viruses, and to detect viruses in samples.
摘要翻译： 可以通过使用某些毒素如溶血素，败血症梭菌的α-毒素或肠球蛋白来减少包含糖基磷脂酰肌醇 - 锚定蛋白的包膜病毒群体的感染性。 与糖基磷脂酰肌醇 - 锚定蛋白结合的毒素使这种病毒失活。 毒素可用于产生减毒的病毒疫苗，以清除这些病毒的血液制品，细胞或组织，并检测样品中的病毒。
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