公开(公告)号：US08358540B2

公开(公告)日：2013-01-22

申请号：US12686721

申请日：2010-01-13

申请人： Dzung H. Nguyen

发明人： Dzung H. Nguyen

IPC分类号： G11C11/34

CPC分类号： G11C16/04 ,  G11C8/08 ,  G11C8/14 ,  G11C16/0483 ,  G11C16/08

摘要： The present disclosure includes methods, devices, and systems for access line biasing. One embodiment includes selecting, using a controller external to the memory device, a particular access line dependent biasing scheme and corresponding bias conditions for use in performing an access operation on an array of memory cells of the memory device, and performing the access operation using the selected particular access line dependent biasing scheme and corresponding bias conditions. In one or more embodiments, the selected particular access line dependent biasing scheme and corresponding bias conditions is selected by the controller external to the memory device based, at least partially, on a target access line of the array.

摘要翻译： 本公开包括用于接入线偏置的方法，设备和系统。 一个实施例包括：使用存储器设备外部的控制器选择特定的访问线路依赖偏置方案和相应的偏置条件，以用于对存储器件的存储器单元阵列执行访问操作，以及使用 所选择的特定接入线相关偏置方案和相应的偏置条件。 在一个或多个实施例中，所选择的特定访问线路依赖偏置方案和对应的偏置条件由存储器设备外部的至少部分地基于阵列的目标访问线路选择。

公开(公告)号：US20120221779A1

公开(公告)日：2012-08-30

申请号：US13464531

申请日：2012-05-04

申请人： Dzung H. Nguyen ,  Benjamin Louie ,  Hagop A. Nazarian ,  Aaron Yip ,  Jin-Man Han

发明人： Dzung H. Nguyen ,  Benjamin Louie ,  Hagop A. Nazarian ,  Aaron Yip ,  Jin-Man Han

IPC分类号： G06F12/00

CPC分类号： G11C16/10

摘要： A target memory cell of a memory device is programmed by applying a programming voltage to a word line that includes the target memory cell, determining whether the target memory cell is programmed, and increasing the programming voltage by a step voltage if it is determined that the target memory cell is not programmed. An initial programming voltage and the step voltage are each selectable after fabrication of the memory device.

摘要翻译： 通过将编程电压施加到包括目标存储器单元的字线，确定目标存储器单元是否被编程来编程存储器件的目标存储器单元，并且如果确定所述编程电压被确定为 目标存储单元未编程。 在制造存储器件之后，可以选择初始编程电压和阶跃电压。

公开(公告)号：US20100124133A1

公开(公告)日：2010-05-20

申请号：US12274426

申请日：2008-11-20

申请人： Vishal Sarin ,  Dzung H. Nguyen ,  William H. Radke

发明人： Vishal Sarin ,  Dzung H. Nguyen ,  William H. Radke

IPC分类号： G11C29/00 ,  G11C8/00

CPC分类号： G11C29/04 ,  G11C29/808 ,  G11C29/82 ,  G11C29/848

摘要： Electronic systems and methods of operating memory devices are provided. In one such embodiment, a memory device receives an external address that addresses a non-defective memory block of a sequence of memory blocks of the memory device in place of a defective memory block of the sequence of memory blocks such that the non-defective memory block replaces the defective memory block. The non-defective memory block is proximate non-defective memory block following the defective memory block in the sequence of memory blocks that is available to replace the defective memory block.

摘要翻译： 提供了操作存储器件的电子系统和方法。 在一个这样的实施例中，存储器设备接收外部地址，其代替存储器块序列的缺陷存储器块来寻址存储器件的一系列存储器块的无缺陷存储器块，使得无缺陷存储器 块代替有缺陷的内存块。 在缺陷存储器块之后的无缺陷存储器块是可用于替换有缺陷的存储器块的存储器块序列中的缺陷存储器块之后的非缺陷存储块。

公开(公告)号：US07525842B2

公开(公告)日：2009-04-28

申请号：US11657950

申请日：2007-01-25

申请人： Dzung H. Nguyen ,  Frankie F. Roohparvar

发明人： Dzung H. Nguyen ,  Frankie F. Roohparvar

IPC分类号： G11C16/06

CPC分类号： G11C16/0483 ,  G11C16/26

摘要： A method of reading sequential pages of flash memory from alternating memory blocks comprises loading data from a first page into a first primary data cache and a second page into a second primary data cache simultaneously, the first and second pages loaded from different blocks of flash memory. Data from the first primary data cache is stored in a first secondary data cache, and data from the second primary data cache is stored in a second secondary data cache. Data is sequentially provided from the first and second secondary data caches by a multiplexer coupled to the first and second data caches.

摘要翻译： 从交替的存储器块读取闪存的顺序页面的方法包括将数据从第一页面加载到第一主数据高速缓存和第二页面中同时加载到第二主数据高速缓存中，从不同的闪存块加载的第一页和第二页 。 来自第一主数据高速缓存的数据被存储在第一辅助数据高速缓存中，并且来自第二主数据高速缓存的数据被存储在第二次数据高速缓存中。 通过耦合到第一和第二数据高速缓存的多路复用器从第一和第二辅助数据高速缓存顺序地提供数据。

公开(公告)号：US06982905B2

公开(公告)日：2006-01-03

申请号：US10682585

申请日：2003-10-09

申请人： Dzung H. Nguyen

发明人： Dzung H. Nguyen

IPC分类号： G11C16/04

CPC分类号： G11C16/26

摘要： The method for reading/verifying a NAND flash memory device alternates the select gate biasing in response to the position of the cell to be read. If the cell is closer to the top of the column, the SG(D) line is biased prior to the SG(S) line. If the cell is closer to the bottom of the column, the SG(S) line is biased prior to the SG(D) line.

摘要翻译： 用于读取/验证NAND闪速存储器件的方法响应于要读取的单元的位置而交替选择栅极偏置。 如果电池更靠近色谱柱的顶部，SG（D）线在SG（S）线之前被偏置。 如果电池更靠近色谱柱的底部，SG（S）线在SG（D）线之前被偏置。

公开(公告)号：US06930536B2

公开(公告)日：2005-08-16

申请号：US10701141

申请日：2003-11-04

申请人： Hagop A. Nazarian ,  Dzung H. Nguyen

发明人： Hagop A. Nazarian ,  Dzung H. Nguyen

IPC分类号： G05F1/10 ,  G11C5/14 ,  G11C11/34 ,  G11C16/08 ,  G11C16/30 ,  H02M3/07

CPC分类号： G11C5/145 ,  G11C16/08 ,  G11C16/30 ,  H02M3/073

摘要： Voltage boosters or pass circuits for generating a boosted voltage are advantageous in the decoding and programming of memory devices and, in particular, NAND flash memory devices. The boosted voltage can be used as a gate voltage for a pass gate providing programming voltages to a selected block of memory cells, such as in a NAND flash memory array. The pass circuits facilitate the elimination of high-voltage p-channel devices by providing a boosted voltage using n-channel devices. The pass circuits further permit control of multiple pass gates using a single boosted voltage source.

摘要翻译： 用于产生升压电压的电压增压器或通过电路在存储器件，特别是NAND闪速存储器件的解码和编程方面是有利的。 升压电压可以用作提供编程电压的通过栅极的栅极电压，所述编程电压例如在NAND闪存阵列中的所选择的存储单元块中。 通过电路通过使用n沟道器件提供升压电压来促进高压p沟道器件的消除。 通过电路还允许使用单个升压电压源来控制多通道门控。

公开(公告)号：US08446787B2

公开(公告)日：2013-05-21

申请号：US12274426

申请日：2008-11-20

申请人： Vishal Sarin ,  Dzung H. Nguyen ,  William H. Radke

发明人： Vishal Sarin ,  Dzung H. Nguyen ,  William H. Radke

IPC分类号： G11C29/08

CPC分类号： G11C29/04 ,  G11C29/808 ,  G11C29/82 ,  G11C29/848

摘要： Electronic systems and methods of operating memory devices are provided. In one such embodiment, a memory device receives an external address that addresses a non-defective memory block of a sequence of memory blocks of the memory device in place of a defective memory block of the sequence of memory blocks such that the non-defective memory block replaces the defective memory block. The non-defective memory block is proximate non-defective memory block following the defective memory block in the sequence of memory blocks that is available to replace the defective memory block.

摘要翻译： 提供了操作存储器件的电子系统和方法。 在一个这样的实施例中，存储器设备接收外部地址，其代替存储器块序列的缺陷存储器块来寻址存储器件的一系列存储器块的无缺陷存储器块，使得无缺陷存储器 块代替有缺陷的内存块。 在缺陷存储器块之后的无缺陷存储器块是可用于替换有缺陷的存储器块的存储器块序列中的缺陷存储器块之后的非缺陷存储块。

公开(公告)号：US08295109B2

公开(公告)日：2012-10-23

申请号：US13017168

申请日：2011-01-31

申请人： Vishal Sarin ,  William H. Radke ,  Dzung H. Nguyen

发明人： Vishal Sarin ,  William H. Radke ,  Dzung H. Nguyen

IPC分类号： G11C29/00

CPC分类号： G11C29/848

摘要： Controllers and memory devices are provided. In an embodiment, a controller is configured to address a non-defective column of memory cells of a memory device in place of a defective column of memory cells of the memory device in response to receiving an address of the defective column of memory cells from the memory device. In another embodiment, a memory device has columns of memory cells and is configured to receive an external address that addresses a non-defective column of memory cells of a sequence of columns of memory cells of the memory device in place of a defective column of memory cells of the sequence of columns of memory cells such that the non-defective column replaces the defective column. The non-defective column is a proximate non-defective column following the defective column in the sequence of columns that is available to replace the defective column.

摘要翻译： 提供控制器和存储器件。 在一个实施例中，控制器被配置为响应于接收来自存储器单元的存储器单元的缺陷列的地址，来代替存储器件的存储器单元的无缺陷列来代替存储器件的存储器单元的缺陷列 存储设备。 在另一个实施例中，存储器设备具有存储单元的列，并且被配置为接收寻址存储器件的存储器单元列序列的无缺陷列的存储器单元的外部地址，而不是缺陷存储器列 存储单元列的序列的单元，使得无缺陷列替代缺陷列。 无缺陷列是可用于替换缺陷列的列序列中的缺陷列之后的邻近无缺陷列。

公开(公告)号：US20110222353A1

公开(公告)日：2011-09-15

申请号：US12720239

申请日：2010-03-09

申请人： Jonathan Pabustan ,  Vishal Sarin ,  Dzung H. Nguyen

发明人： Jonathan Pabustan ,  Vishal Sarin ,  Dzung H. Nguyen

IPC分类号： G11C16/04 ,  G11C16/06 ,  G11C7/10

CPC分类号： G06F3/0613 ,  G06F3/0655 ,  G06F3/0679 ,  G11C16/08 ,  G11C16/10 ,  G11C16/26 ,  G11C16/32 ,  G11C16/3454 ,  G11C16/3459

摘要： Methods for sensing, method for programming, memory devices, and memory systems are disclosed. In one such method for sensing, a counting circuit generates a count output and a translated count output. The count output is converted into a time varying voltage that biases a word line coupled to memory cells being sensed. Target data for each memory cell is stored in a data cache associated with that particular memory cell. When it is detected that a memory cell has turned on, the translated count output associated with the count output that is indicative of the voltage level that turned on the memory cell is compared to the target data. The comparison determines the state of the memory cell.

摘要翻译： 公开了感测方法，编程方法，存储器件和存储器系统。 在一种用于感测的方法中，计数电路产生计数输出和转换计数输出。 计数输出被转换成时变电压，该电压偏置耦合到被感测的存储器单元的字线。 每个存储器单元的目标数据被存储在与该特定存储器单元相关联的数据高速缓存器中。 当检测到存储器单元已经接通时，将与指示存储器单元接通的电压电平的计数输出相关联的转换计数输出与目标数据进行比较。 比较确定存储单元的状态。

公开(公告)号：US07903463B2

公开(公告)日：2011-03-08

申请号：US12425200

申请日：2009-04-16

申请人： Dzung H. Nguyen ,  Frankie F. Roohparvar

发明人： Dzung H. Nguyen ,  Frankie F. Roohparvar

IPC分类号： G11C16/04

CPC分类号： G11C16/0483 ,  G11C16/26

摘要： A method of reading sequential pages of flash memory from alternating memory blocks comprises loading data from a first page into a first primary data cache and a second page into a second primary data cache simultaneously, the first and second pages loaded from different blocks of flash memory. Data from the first primary data cache is stored in a first secondary data cache, and data from the second primary data cache is stored in a second secondary data cache. Data is sequentially provided from the first and second secondary data caches by a multiplexer coupled to the first and second data caches.

摘要翻译： 从交替的存储器块读取闪存的顺序页面的方法包括将数据从第一页面加载到第一主数据高速缓存和第二页面中同时加载到第二主数据高速缓存中，从不同的闪存块加载的第一页和第二页 。 来自第一主数据高速缓存的数据被存储在第一辅助数据高速缓存中，并且来自第二主数据高速缓存的数据被存储在第二次数据高速缓存中。 通过耦合到第一和第二数据高速缓存的多路复用器从第一和第二辅助数据高速缓存顺序地提供数据。