公开(公告)号：US06873184B1

公开(公告)日：2005-03-29

申请号：US10653802

申请日：2003-09-03

申请人： Brian D. McMinn ,  Michael K. Ciraula ,  Gerald D. Zuraski, Jr.

发明人： Brian D. McMinn ,  Michael K. Ciraula ,  Gerald D. Zuraski, Jr.

IPC分类号： G06F5/10 ,  G06F12/00 ,  G06F12/08

CPC分类号： G06F5/10 ,  G06F12/0862 ,  G06F2205/106

摘要： An apparatus comprises a buffer comprising a plurality of entries, an insert pointer, a delete pointer, a plurality of first control circuits coupled to the buffer, and a second control circuit coupled to the buffer. The entries are logically divided into a plurality of groups. Each of the first control circuits corresponds to a respective group and selects an entry from the respective group for potential reading from the buffer. Furthermore, each of the first control circuits, in the event that the delete pointer indicates a first entry in the respective group and the insert pointer wraps around the buffer and indicates a second entry in the respective group, selects the first entry if the first entry is eligible for selection. The second control circuit selects a first group, and the entry selected from the first group by the first control circuits is the entry read from the buffer.

摘要翻译： 一种装置包括缓冲器，该缓冲器包括多个条目，插入指针，删除指针，耦合到缓冲器的多个第一控制电路以及耦合到缓冲器的第二控制电路。 这些条目在逻辑上分为多个组。 每个第一控制电路对应于相应的组，并从相应组中选择一个来自缓冲器的电位读取的条目。 此外，在删除指针指示相应组中的第一条目并且插入指针围绕缓冲器包围并指示相应组中的第二条目的情况下，每个第一控制电路选择第一条目，如果第一条目 有资格选择。 第二控制电路选择第一组，并且由第一控制电路从第一组中选择的条目是从缓冲器读取的条目。

公开(公告)号：US06711696B1

公开(公告)日：2004-03-23

申请号：US09637985

申请日：2000-08-11

申请人： Michael E. Bates ,  Brian D. McMinn

发明人： Michael E. Bates ,  Brian D. McMinn

IPC分类号： G06F112

CPC分类号： G06F5/14 ,  G06F1/12 ,  H04L7/0012

摘要： A method and related system for transferring data between systems having different clock domains. A skip signal generation circuit calculates substantially simultaneously with the transfer of data which signals of the faster clock domain should be skipped to ensure proper operation. The skip signal generation circuit makes this determination using values representing the faster and slower frequencies of each clock domain. These values are obtained either from preset values integrated in some form onto the microprocessor substrate, or may be written to the microprocessor by external circuitry and software. The skip signal generation circuit is capable of calculating skip patterns for any ratio of faster to slower frequency and is not constrained to have integer or half-integer ratios of the faster and slower clock domains.

摘要翻译： 一种用于在具有不同时钟域的系统之间传送数据的方法和相关系统。 跳跃信号生成电路基本上与数据的传送同时计算应该跳过较快时钟域的信号以确保正确的操作。 跳过信号生成电路使用表示每个时钟域的更快和更慢频率的值进行该确定。 这些值可以从以某种形式集成到微处理器基板上的预设值获得，或者可以通过外部电路和软件写入微处理器。 跳过信号产生电路能够计算出快速到慢速频率的任何比率的跳跃模式，并且不被限制为具有较快和较慢时钟域的整数或半整数比。

公开(公告)号：US6032252A

公开(公告)日：2000-02-29

申请号：US959631

申请日：1997-10-28

申请人： Anthony M. Petro ,  Brian D. McMinn

发明人： Anthony M. Petro ,  Brian D. McMinn

IPC分类号： G06F9/308 ,  G06F9/32 ,  G06F9/38 ,  G06F9/40

CPC分类号： G06F9/382 ,  G06F9/30018 ,  G06F9/325 ,  G06F9/3861 ,  G06F9/3885

摘要： A superscalar microprocessor implements a repeated string instruction by putting the microcode unit in a continuous loop. The microcode sequence that implements the repeated string operation includes a conditional-exit instruction rather than a conditional branch and decrement microcode instruction. A conditional-exit instruction decrements a loop count value and conveys a termination signal to a microcode unit when a termination condition is detected. Because several iterations of the instructions that implement the string instruction may be dispatched before the conditional-exit instruction is evaluated, the additional iterations of the microcode loop are canceled. By eliminating the conditional branch and decrement microcode instruction, a loop iteration may be executed in a single clock cycle by three functional units.

摘要翻译： 超标量微处理器通过将微代码单元置于连续循环中来实现重复的串指令。 实现重复字符串操作的微代码序列包括条件退出指令而不是条件分支和递减微码指令。 当检测到终止条件时，条件退出指令递减循环计数值并将终止信号传送到微代码单元。 因为在条件退出指令被评估之前可以调度实现字符串指令的指令的几次迭代，所以微代码循环的附加迭代被取消。 通过消除条件分支和递减微代码指令，循环迭代可以在单个时钟周期内由三个功能单元执行。

公开(公告)号：US5727177A

公开(公告)日：1998-03-10

申请号：US623756

申请日：1996-03-29

申请人： Brian D. McMinn ,  Robert D. Gowin, Jr.

发明人： Brian D. McMinn ,  Robert D. Gowin, Jr.

IPC分类号： G06F9/30 ,  G06F9/32 ,  G06F9/38

CPC分类号： G06F9/30112 ,  G06F9/3001 ,  G06F9/30054 ,  G06F9/30101 ,  G06F9/3836 ,  G06F9/384 ,  G06F9/3855 ,  G06F9/3857

摘要： A superscalar processor provides register renaming using a reorder buffer includes special registers for handling predefined special instructions that operate on an odd-width data word. The superscalar processor includes a reorder buffer which stores result data having a predetermined standard bit-width. One or more instructions that generally occur only occasionally have a result data width that is substantially larger than the standard bit-width. The reorder buffer stores data of the standard bit-width and the occasional large bit-width in a storage that includes a plurality of standard-width storage elements in a first-in-first-out FIFO reorder buffer queue and a separate buffer that is specifically allocated for storing an extended result element. An extended result element includes a portion of a large bit-width result in excess of the standard bit-width result size.

摘要翻译： 超标量处理器使用重排序缓冲器提供寄存器重命名，包括用于处理在奇数数据字上操作的预定义特殊指令的专用寄存器。 超标量处理器包括重排序缓冲器，其存储具有预定的标准位宽的结果数据。 通常仅偶尔出现的一个或多个指令的结果数据宽度明显大于标准位宽。 重排序缓冲器将标准位宽和偶然的大位宽的数据存储在包括先进先出FIFO重排缓冲器队列中的多个标准宽度存储元件的存储器中，并且单独的缓冲器是 专门用于存储扩展结果元素。 扩展结果元素包括超过标准位宽结果大小的大位宽结果的一部分。

公开(公告)号：US5646893A

公开(公告)日：1997-07-08

申请号：US525431

申请日：1995-09-07

申请人： Brian D. McMinn ,  R. Tod Calvin

发明人： Brian D. McMinn ,  R. Tod Calvin

IPC分类号： G11C8/00 ,  G11C8/16 ,  G11C7/00

CPC分类号： G11C8/00 ,  G11C8/16

摘要： A read line for a column of memory cells within an array is divided into a first read line segment, a first read buffer, and a second read line segment. Both the first and second read line segments occupy a single wiring channel. When reading a memory cell connected to the first read line segment, the level of the first read line segment is sensed by the first read buffer and conveyed to a column read output node by way of the second read line segment and an associated second read buffer. Alternatively, when reading a memory cell connected to the second read line segment, the first read buffer is disabled, thus adopting a high impedance output, and the level of the second read line segment is sensed by the second read buffer and conveyed to the column read output node. Each of the first and second read line segments have less capacitive loading than a single read line, which results in lower power and faster read access times. Further, when reading a memory cell coupled to the second read line segment, the first read line segment remains in a precharged state, conserving power even more. Consequently, when used as part of a multiport register file within a processor, power is reduced by implementing registers having a high frequency of reference as memory cells coupled to the second read line segment.

摘要翻译： 阵列内的一列存储单元的读取行被划分为第一读取段，第一读取缓冲区和第二读取段。 第一和第二读取线段都占用单个布线通道。 当读取连接到第一读取线段的存储单元时，第一读取线段的电平由第一读取缓冲器感测并通过第二读取线段和相关联的第二读取缓冲器被传送到列读取输出节点 。 或者，当读取连接到第二读取线段的存储单元时，第一读取缓冲器被禁用，因此采用高阻抗输出，并且第二读取线段的电平由第二读取缓冲器感测并传送到列 读输出节点。 第一和第二读线段中的每一个具有比单个读取线更小的电容负载，这导致较低的功率和更快的读取访问时间。 此外，当读取耦合到第二读取线段的存储单元时，第一读取线段保持在预充电状态，甚至更节省功率。 因此，当用作处理器内的多端口寄存器文件的一部分时，通过实现具有高频率参考的寄存器作为耦合到第二读线段的存储器单元来减小功率。

公开(公告)号：US5327571A

公开(公告)日：1994-07-05

申请号：US104398

申请日：1993-08-10

申请人： Brian D. McMinn ,  Robert H. Perlman ,  Prem Sobel

发明人： Brian D. McMinn ,  Robert H. Perlman ,  Prem Sobel

IPC分类号： G06F9/30 ,  G06F9/32 ,  G06F9/315 ,  G06F9/312

CPC分类号： G06F9/30094 ,  G06F9/30101

摘要： A processor for collecting boolean conditions of multiple operations includes a condition collection register which may be written and read in parallel or written serially and into which a single bit is shifted from either the left or the right, and a processor instruction decoder that decodes one operand register addresses as a read address for the condition collection register, and three operand register addresses as a write address for said condition collection register.

摘要翻译： 用于收集多个操作的布尔条件的处理器包括条件收集寄存器，其可以被并行地写入和读取，串行地写入，并且单个位从左或右移位到其中，并且处理器指令解码器解码一个操作数 寄存器地址作为条件收集寄存器的读取地址，三个操作数寄存器地址作为所述条件收集寄存器的写入地址。

公开(公告)号：US5059818A

公开(公告)日：1991-10-22

申请号：US532311

申请日：1990-06-01

申请人： David B. Witt ,  Brian D. McMinn

发明人： David B. Witt ,  Brian D. McMinn

IPC分类号： G06F1/06 ,  G06F1/08

CPC分类号： G06F1/08

摘要： There is disclosed a self-regulating clock generator for providing an output clock signal to clock a CMOS microprocessor. The output clock signal has first and second phases of sufficient length to accommodate microprocessor speed paths and is provided in response to an input clock signal having a frequency and a duty cycle within a wide range of frequencies and duty cycles. The clock generator includes a latch arranged to be set and reset by the input clock signal and having an output for providing the output clock signal. A delay circuit is coupled to the latch output and enables the setting and resetting of the latch to establish the phase lengths. Also disclosed is a second clock generator which includes a pair of latches and a pair of delay circuits for providing an output clock signal having first and second phases of different lengths.

公开(公告)号：US5058048A

公开(公告)日：1991-10-15

申请号：US503819

申请日：1990-04-02

申请人： Smeeta Gupta ,  Robert M. Perlman ,  Thomas W. Lynch ,  Brian D. McMinn

发明人： Smeeta Gupta ,  Robert M. Perlman ,  Thomas W. Lynch ,  Brian D. McMinn

IPC分类号： G06F7/00 ,  G06F7/485 ,  G06F7/53 ,  G06F7/57 ,  G06F7/76 ,  G06F9/38

CPC分类号： G06F7/483 ,  G06F7/49936

摘要： A floating point processor for performing arithmetic operations on floating point numbers includes a first arithmetic operation unit configured to operate on normalized numbers and a second arithmetic operation unit which includes a denormalizer for denormalizing normalized numbers and a normalizer for normalizing denormalized numbers. Each arithmetic operation unit has first and second inputs for receiving first and second operands, respectively, and an output for transmitting a result of the arithmetic operation. When an denormalized operand is presented as an input to the arithmetic operation unit configured to operate on normalized numbers, the denormalized input operand is redirected through the second arithmetic unit for normalization of the denormalized operand. The first arithmetic operation unit then performs its arithmetic operation using the normalized input operands. The result of the arithmetic operation is then analyzed to determine whether it has a zero or negative exponent. If the result has a zero or negative exponent, the result is directed through the second arithmetic unit a second time so that the result is denormalized. The denormalized result is then output.