公开(公告)号：US20100117164A1

公开(公告)日：2010-05-13

申请号：US12426950

申请日：2009-04-20

Applicant: Wei-Chieh Lin ,  Ho-Tai Chen ,  Hsin-Yu Hsu

Inventor： Wei-Chieh Lin ,  Ho-Tai Chen ,  Hsin-Yu Hsu

IPC: H01L29/78

CPC classification number: H01L29/1041 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/7802

Abstract: A high-voltage MOS transistor device includes a substrate, a semiconductor layer formed on the substrate, a gate structure having an opening, formed on the semiconductor layer, a first source/drain region of a first conductivity type formed in the semiconductor layer at one side of the gate structure, a second source/drain region of the first conductivity type formed in the semiconductor layer at the other side of the gate structure, a channel region disposed by a dopant of the first conductivity type between the first source/drain region and the second source/drain region, and a doping region of the first conductivity type formed in the channel region and under the opening of the gate structure, wherein a doping concentration of the doping region is higher than a doping concentration of the channel region.

Abstract translation: 高电压MOS晶体管器件包括衬底，形成在衬底上的半导体层，形成在半导体层上的具有开口的栅极结构，形成在半导体层中的第一导电类型的第一源极/漏极区域 在栅极结构的另一侧形成在半导体层中的第一导电类型的第二源极/漏极区，由第一导电类型的掺杂剂在第一源极/漏极区域之间设置的沟道区域 和第二源极/漏极区域以及形成在沟道区域中的栅极结构的开口处的第一导电类型的掺杂区域，其中掺杂区域的掺杂浓度高于沟道区域的掺杂浓度。

公开(公告)号：US20100055857A1

公开(公告)日：2010-03-04

申请号：US12334492

申请日：2008-12-14

Applicant: Wei-Chieh Lin ,  Hsin-Yu Hsu ,  Hsin-Yen Chiu ,  Shih-Chieh Hung ,  Ho-Tai Chen ,  Jen-Hao Yeh ,  Li-Cheng Lin

Inventor： Wei-Chieh Lin ,  Hsin-Yu Hsu ,  Hsin-Yen Chiu ,  Shih-Chieh Hung ,  Ho-Tai Chen ,  Jen-Hao Yeh ,  Li-Cheng Lin

IPC: H01L21/336

CPC classification number: H01L29/7813 ,  H01L21/26586 ,  H01L29/4236 ,  H01L29/456 ,  H01L29/66734

Abstract: A method of forming a power device includes providing a substrate, a semiconductor layer having at least a trench and being disposed on the substrate, a gate insulating layer covering the semiconductor layer, and a conductive material disposed in the trench, performing an ion implantation process to from a body layer, performing a tilted ion implantation process to from a heavy doped region, forming a first dielectric layer overall, performing a chemical mechanical polishing process until the body layer disposed under the heavy doped region is exposed to form source regions on the opposite sides of the trench, and forming a source trace directly covering the source regions disposed on the opposite sides of the trench.

Abstract translation: 一种形成功率器件的方法包括提供衬底，至少具有沟槽并设置在衬底上的半导体层，覆盖半导体层的栅极绝缘层和设置在沟槽中的导电材料，执行离子注入工艺 从体层进行倾斜的离子注入工艺，从重掺杂区域进行倾斜的离子注入工艺，整体形成第一介电层，进行化学机械抛光工艺，直到布置在重掺杂区域之下的体层露出，形成源区 并且形成直接覆盖设置在沟槽的相对侧上的源极区域的源极迹线。

公开(公告)号：US20090117700A1

公开(公告)日：2009-05-07

申请号：US12135217

申请日：2008-06-09

Applicant: Wei-Chieh Lin ,  Jen-Hao Yeh ,  Ming-Jang Lin

Inventor： Wei-Chieh Lin ,  Jen-Hao Yeh ,  Ming-Jang Lin

IPC: H01L21/336

CPC classification number: H01L29/7813 ,  H01L29/0661 ,  H01L29/1095 ,  H01L29/41741 ,  H01L29/41766

Abstract: A method for manufacturing a trench power transistor includes providing a substrate, forming an epitaxy layer on the substrate, performing a dry etching process on the epitaxy layer for generating a first trench, forming a gate oxide layer in the first trench and depositing poly-Si on the gate oxide layer in the first trench, performing a boron implant process on regions outside the first trench and inside the epitaxy layer, performing an arsenic implant process on regions beside the first trench and inside the epitaxy layer, depositing a first dielectric material on the surface of the epitaxy layer, performing a dry etching process on the epitaxy layer for generating a second trench, depositing a conductive material in the second trench for forming a p-well junction on sidewalls of the second trench, and performing a wet immersion process for forming a contact hole, and depositing frontside and backside metal.

Abstract translation: 一种制造沟槽功率晶体管的方法，包括提供衬底，在衬底上形成外延层，在用于产生第一沟槽的外延层上进行干蚀刻工艺，在第一沟槽中形成栅极氧化层并沉积多晶硅 在所述第一沟槽中的栅极氧化层上，对所述第一沟槽外部的区域和所述外延层内部的区域进行硼注入工艺，对所述第一沟槽旁边的区域和所述外延层内部的区域执行砷注入工艺，将第一介电材料沉积在 外延层的表面，在用于产生第二沟槽的外延层上进行干蚀刻处理，在第二沟槽中沉积导电材料，以在第二沟槽的侧壁上形成p阱结，并执行湿式浸渍工艺 用于形成接触孔，以及沉积前侧和后侧金属。

公开(公告)号：US09166037B2

公开(公告)日：2015-10-20

申请号：US13101155

申请日：2011-05-05

Applicant: Wei-Chieh Lin

Inventor： Wei-Chieh Lin

IPC: H01L27/02 ,  H01L29/78 ,  H01L29/66 ,  H01L29/06 ,  H01L29/417

CPC classification number: H01L29/7813 ,  H01L27/0248 ,  H01L27/0255 ,  H01L27/0259 ,  H01L29/0653 ,  H01L29/41766 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7808

Abstract: A power semiconductor device with an electrostatic discharge (ESD) structure includes an N-type semiconductor substrate, at least one ESD device, and at least one trench type transistor device. The N-type semiconductor has at least two trenches, and the ESD device is disposed in the N-type semiconductor substrate between the trenches. The ESD device includes a P-type first doped region, and an N-type second doped region and an N-type third doped region disposed in the P-type first doped region. The N-type second doped region is electrically connected to a gate of the trench type transistor device, and the N-type third doped region is electrically connected to a drain of the trench type transistor device.

Abstract translation: 具有静电放电（ESD）结构的功率半导体器件包括N型半导体衬底，至少一个ESD器件和至少一个沟槽型晶体管器件。 N型半导体具有至少两个沟槽，并且ESD器件设置在沟槽之间的N型半导体衬底中。 ESD器件包括P型第一掺杂区域和设置在P型第一掺杂区域中的N型第二掺杂区域和N型第三掺杂区域。 N型第二掺杂区域电连接到沟槽型晶体管器件的栅极，并且N型第三掺杂区域电连接到沟槽型晶体管器件的漏极。

公开(公告)号：US08680609B2

公开(公告)日：2014-03-25

申请号：US13091160

申请日：2011-04-21

Applicant: Wei-Chieh Lin ,  Jia-Fu Lin

Inventor： Wei-Chieh Lin ,  Jia-Fu Lin

IPC: H01L29/76

CPC classification number: H01L29/7828 ,  H01L21/26586 ,  H01L29/41766 ,  H01L29/66666

Abstract: A manufacturing method of a depletion mode trench semiconductor device includes following steps. Firstly, a substrate including a drift epitaxial layer disposed thereon is provided. A trench is disposed in the drift epitaxial layer. A gate dielectric layer is formed on an inner sidewall of the trench and an upper surface of the drift epitaxial layer. A base doped region is formed in the drift epitaxial layer and adjacent to a side of the trench. A thin doped region is formed and conformally contacts the gate dielectric layer. A gate material layer is formed to fill the trench. A source doped region is formed in the base doped region, and the source doped region overlaps the thin doped region at a side of the trench. Finally, a contact doped region is formed to overlap the thin doped region, and the contact doped region is adjacent to the source doped region.

Abstract translation: 耗尽型沟槽半导体器件的制造方法包括以下步骤。 首先，提供包括设置在其上的漂移外延层的衬底。 沟槽设置在漂移外延层中。 栅极电介质层形成在沟槽的内侧壁和漂移外延层的上表面上。 基极掺杂区域形成在漂移外延层中并与沟槽的一侧相邻。 形成薄的掺杂区域并保形地接触栅极电介质层。 形成栅极材料层以填充沟槽。 源极掺杂区域形成在基极掺杂区域中，并且源极掺杂区域与沟槽侧面的薄掺杂区域重叠。 最后，形成接触掺杂区域以与薄掺杂区域重叠，并且接触掺杂区域与源极掺杂区域相邻。

公开(公告)号：US08564097B2

公开(公告)日：2013-10-22

申请号：US12760754

申请日：2010-04-15

Applicant: Florin Udrea ,  Chih-Wei Hsu ,  Wei-Chieh Lin

Inventor： Florin Udrea ,  Chih-Wei Hsu ,  Wei-Chieh Lin

IPC: H01L27/082

CPC classification number: H01L29/7397 ,  H01L29/0834 ,  H01L29/66348

Abstract: An insulated gate bipolar transistor (IGBT) is provided comprising a semiconductor substrate having the following regions in sequence: (i) a first region of a first conductive type having opposing surfaces, a column region of a second conductive type within the first region extending from a first of said opposing surfaces; (ii) a drift region of the second conductive type; (iii) a second region of the first conductive type, and (iv) a third region of the second conductive type. There is provided a gate electrode disposed to form a channel between the third region and the drift region, a first electrode operatively connected to the second region and the third region, a second electrode operatively connected to the first region and the column region. The arrangement of the IGBT is such that the column region is spaced from a second surface of the opposing surfaces of the first region, whereby a forward conduction path extends sequentially through the third region, the second region, the drift region, and the first region, and whereby a reverse conduction path extends sequentially through the second region, the drift region, the first region and the column region. Reverse conduction of the IGBT occurs through a thyristor structure which is embedded in the IGBT. Such an IGBT structure is advantageous over a reverse conducting IGBT structure in which an anti-parallel diode is integrated or embedded because it provides improved reverse conduction and snapback performance.

Abstract translation: 提供了绝缘栅双极晶体管（IGBT），其包括依次具有以下区域的半导体衬底：（i）具有相对表面的第一导电类型的第一区域，在第一区域内延伸的第二导电类型的列区域 所述相对表面中的第一个; （ii）第二导电类型的漂移区域; （iii）第一导电类型的第二区域，和（iv）第二导电类型的第三区域。 提供了一个设置成在第三区域和漂移区域之间形成通道的栅电极，可操作地连接到第二区域和第三区域的第一电极，可操作地连接到第一区域和列区域的第二电极。 IGBT的布置使得列区域与第一区域的相对表面的第二表面间隔开，由此正向导电路径依次延伸穿过第三区域，第二区域，漂移区域和第一区域 并且由此反向传导路径依次延伸穿过第二区域，漂移区域，第一区域和列区域。 IGBT的反向导通通过嵌入在IGBT中的晶闸管结构发生。 这种IGBT结构优于反并联二极管集成或嵌入的反向导通IGBT结构，因为它提供改进的反向导通和快速恢复性能。

公开(公告)号：US20130049106A1

公开(公告)日：2013-02-28

申请号：US13523841

申请日：2012-06-14

Applicant: Wei-Chieh Lin

Inventor： Wei-Chieh Lin

IPC: H01L27/092 ,  H01L21/8238

CPC classification number: H01L29/7813 ,  H01L29/41766 ,  H01L29/42368 ,  H01L29/66719 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7831

Abstract: The present invention provides a bidirectional semiconductor device including a semiconductor substrate having a first conductive type, a first doped base region and a second doped base region having a second conductive type, and a gate insulating layer. The semiconductor substrate has a first trench, and the first doped base region and the second doped base region are respectively disposed in the semiconductor substrate at two sides of the first trench. The gate insulating layer covers a surface of the first trench, and the gate insulating layer has a first part adjacent to the first doped base region, a second part adjacent to the second doped base region, and a third part disposed at a corner between a bottom and a sidewall of the first trench. A thickness of the first part and a thickness of the second part are less than a thickness of the third part.

Abstract translation: 本发明提供了一种双向半导体器件，其包括具有第一导电类型，第一掺杂基极区域和具有第二导电类型的第二掺杂基极区域的半导体衬底和栅极绝缘层。 半导体衬底具有第一沟槽，并且第一掺杂基极区域和第二掺杂基极区域分别设置在第一沟槽的两侧的半导体衬底中。 栅极绝缘层覆盖第一沟槽的表面，并且栅极绝缘层具有与第一掺杂基极区相邻的第一部分，与第二掺杂基极区相邻的第二部分，以及设置在第二部分 底部和第一沟槽的侧壁。 第一部分的厚度和第二部分的厚度小于第三部分的厚度。

公开(公告)号：US08319284B2

公开(公告)日：2012-11-27

申请号：US12839426

申请日：2010-07-20

Applicant: Wei-Chieh Lin ,  Ho-Tai Chen ,  Jia-Fu Lin ,  Po-Hsien Li

Inventor： Wei-Chieh Lin ,  Ho-Tai Chen ,  Jia-Fu Lin ,  Po-Hsien Li

IPC: H01L29/66

CPC classification number: H01L29/0847 ,  H01L29/0657 ,  H01L29/0878 ,  H01L29/402 ,  H01L29/41725 ,  H01L29/4175 ,  H01L29/41758 ,  H01L29/41766 ,  H01L29/456 ,  H01L29/7816 ,  H01L29/7835

Abstract: A laterally diffused metal-oxide-semiconductor device includes a substrate, a gate dielectric layer, a gate polysilicon layer, a source region, a drain region, a body region, a first drain contact plug, a source polysilicon layer, an insulating layer, and a source metal layer. The source polysilicon layer disposed on the gate dielectric layer above the drain region can serve as a field plate to enhance the breakdown voltage and to increase the drain-to-source capacitance. In addition, the first drain contact plug of the present invention can reduce the drain-to-source on-resistance and the horizontal extension length.

Abstract translation: 横向扩散的金属氧化物半导体器件包括衬底，栅极电介质层，栅极多晶硅层，源极区域，漏极区域，体区域，第一漏极接触插塞，源极多晶硅层，绝缘层， 和源极金属层。 设置在漏极区域上的栅极电介质层上的源极多晶硅层可以用作场板，以增强击穿电压并增加漏极 - 源极电容。 此外，本发明的第一漏极接触插塞可以减小漏极 - 源极导通电阻和水平延长长度。

公开(公告)号：US08242537B2

公开(公告)日：2012-08-14

申请号：US12615278

申请日：2009-11-10

Applicant: Wei-Chieh Lin ,  Jen-Hao Yeh ,  Ho-Tai Chen

Inventor： Wei-Chieh Lin ,  Jen-Hao Yeh ,  Ho-Tai Chen

IPC: H01L29/739 ,  H01L21/331

CPC classification number: H01L29/7397 ,  H01L29/0834 ,  H01L29/1095 ,  H01L29/66348

Abstract: An IGBT with a fast reverse recovery time rectifier includes an N-type drift epitaxial layer, a gate, a gate insulating layer, a P-type doped base region, an N-type doped source region, a P-type doped contact region, and a P-type lightly doped region. The P-type doped base region is disposed in the N-type drift epitaxial layer, and the P-type doped contact region is disposed in the N-type drift epitaxial layer. The P-type lightly doped region is disposed between the P-type contact doped region and the N-type drift epitaxial layer, and is in contact with the N-type drift epitaxial layer.

Abstract translation: 具有快速反向恢复时间整流器的IGBT包括N型漂移外延层，栅极，栅极绝缘层，P型掺杂基极区域，N型掺杂源极区域，P型掺杂接触区域， 和P型轻掺杂区域。 P型掺杂基区设置在N型漂移外延层中，P型掺杂接触区设置在N型漂移外延层中。 P型轻掺杂区域设置在P型接触掺杂区域和N型漂移外延层之间，并与N型漂移外延层接触。

公开(公告)号：US08241978B2

公开(公告)日：2012-08-14

申请号：US12536504

申请日：2009-08-06

Applicant: Wei-Chieh Lin ,  Li-Cheng Lin ,  Hsin-Yu Hsu ,  Ho-Tai Chen ,  Jen-Hao Yeh ,  Guo-Liang Yang ,  Chia-Hui Chen ,  Shih-Chieh Hung

Inventor： Wei-Chieh Lin ,  Li-Cheng Lin ,  Hsin-Yu Hsu ,  Ho-Tai Chen ,  Jen-Hao Yeh ,  Guo-Liang Yang ,  Chia-Hui Chen ,  Shih-Chieh Hung

IPC: H01L27/06 ,  H01L21/336

CPC classification number: H01L27/0629 ,  H01L29/8725

Abstract: A semiconductor device having integrated MOSFET and Schottky diode includes a substrate having a MOSFET region and a Schottky diode region defined thereon; a plurality of first trenches formed in the MOSFET region; and a plurality of second trenches formed in the Schottky diode region. The first trenches respectively including a first insulating layer formed over the sidewalls and bottom of the first trench and a first conductive layer filling the first trench serve as a trenched gate of the trench MOSFET. The second trenches respectively include a second insulating layer formed over the sidewalls and bottom of the second trench and a second conductive layer filling the second trench. A depth and a width of the second trenches are larger than that of the first trenches; and a thickness of the second insulating layer is larger than that of the first insulating layer.

Abstract translation: 具有集成MOSFET和肖特基二极管的半导体器件包括其上限定有MOSFET区和肖特基二极管区的衬底; 形成在所述MOSFET区域中的多个第一沟槽; 以及形成在肖特基二极管区域中的多个第二沟槽。 分别包括形成在第一沟槽的侧壁和底部上的第一绝缘层的第一沟槽和填充第一沟槽的第一导电层用作沟槽MOSFET的沟槽栅极。 第二沟槽分别包括形成在第二沟槽的侧壁和底部上的第二绝缘层和填充第二沟槽的第二导电层。 第二沟槽的深度和宽度大于第一沟槽的深度和宽度; 并且所述第二绝缘层的厚度大于所述第一绝缘层的厚度。