公开(公告)号：US20060046388A1

公开(公告)日：2006-03-02

申请号：US11214247

申请日：2005-08-29

申请人： Young-Sam Park ,  Seung-Beom Yoon ,  Jeong-Uk Han ,  Sung-Taeg Kang ,  Seung-Jin Yang

发明人： Young-Sam Park ,  Seung-Beom Yoon ,  Jeong-Uk Han ,  Sung-Taeg Kang ,  Seung-Jin Yang

IPC分类号： H01L21/336 ,  H01L21/3205 ,  H01L21/8238

CPC分类号： H01L21/28273 ,  H01L29/42324 ,  H01L29/66553 ,  H01L29/66795 ,  H01L29/7851 ,  H01L29/7853 ,  H01L29/7854 ,  H01L29/7881

摘要： A nonvolatile semiconductor device and a method of fabricating the same are provided. The nonvolatile semiconductor device includes a semiconductor body formed on a substrate to be elongated in one direction and having a cross section perpendicular to a main surface of the substrate and elongated direction, the cross section having a predetermined curvature, a channel region partially formed along the circumference of the semiconductor body, a tunneling insulating layer disposed on the channel region, a floating gate disposed on the tunneling insulating layer and electrically insulated from the channel region, an intergate insulating layer disposed on the floating gate, a control gate disposed on the intergate insulating layer and electrically insulated from the floating gate, and source and drain regions which are aligned with both sides of the control gate and formed within the semiconductor body.

摘要翻译： 提供一种非易失性半导体器件及其制造方法。 非易失性半导体器件包括形成在基板上的半导体本体，该半导体本体在一个方向上被延伸并且具有垂直于基板的主表面和细长方向的横截面，该横截面具有预定的曲率， 设置在沟道区域上的隧道绝缘层，设置在隧道绝缘层上并与沟道区电绝缘的浮置栅极，设置在浮动栅极上的栅极间绝缘层，设置在栅极上的控制栅极 绝缘层和与浮置栅极电绝缘的源极和漏极区域，其与控制栅极的两侧对准并形成在半导体本体内。

公开(公告)号：US07932149B2

公开(公告)日：2011-04-26

申请号：US12453676

申请日：2009-05-19

申请人： Jae-Hyun Park ,  Jeong-Uk Han ,  Jae-Min Yu ,  Young-Cheon Jeong ,  Sang-Hoon Park ,  Kwan-Jong Roh ,  Byeong-Cheol Lim ,  Yong-Seok Chung

发明人： Jae-Hyun Park ,  Jeong-Uk Han ,  Jae-Min Yu ,  Young-Cheon Jeong ,  Sang-Hoon Park ,  Kwan-Jong Roh ,  Byeong-Cheol Lim ,  Yong-Seok Chung

IPC分类号： H01L21/336

CPC分类号： H01L29/4234 ,  H01L27/11568 ,  H01L27/11573

摘要： In a method of manufacturing a semiconductor device, a tunnel insulation layer is formed on a substrate. A charge trapping layer is formed on the tunnel insulation layer. A protection layer pattern or a mold is formed on the charge trapping layer. Charge trapping layer patterns are formed on the tunnel insulation layer by etching the charge trapping layer using the protection layer pattern or the mold. The charge trapping layer patterns may be spaced apart from each other. Blocking layers are formed on the charge trapping layer patterns, respectively. A gate electrode is formed on the blocking layers and the tunnel insulation layer using the protection layer pattern or the mold.

摘要翻译： 在制造半导体器件的方法中，在衬底上形成隧道绝缘层。 在隧道绝缘层上形成电荷捕获层。 在电荷捕获层上形成保护层图案或模具。 通过使用保护层图案或模具蚀刻电荷捕获层，在隧道绝缘层上形成电荷俘获层图案。 电荷捕获层图案可以彼此间隔开。 阻挡层分别形成在电荷俘获层图案上。 使用保护层图案或模具在阻挡层和隧道绝缘层上形成栅电极。

公开(公告)号：US20110038210A1

公开(公告)日：2011-02-17

申请号：US12912517

申请日：2010-10-26

申请人： Yong-Kyu Lee ,  Jeong-Uk Han ,  Hee-Seog Jeon ,  Jung-Ho Moon ,  Soung-Youb Ha

发明人： Yong-Kyu Lee ,  Jeong-Uk Han ,  Hee-Seog Jeon ,  Jung-Ho Moon ,  Soung-Youb Ha

IPC分类号： G11C16/26 ,  G11C16/04 ,  G11C16/30

CPC分类号： G11C16/0433 ,  G11C16/26 ,  H01L27/105 ,  H01L27/11526 ,  H01L27/11529

摘要： In a method of reading data in an EEPROM cell, a bit line voltage for reading is applied to the EEPROM cell including a memory transistor and a selection transistor. A first voltage is applied to a sense line of the memory transistor. A second voltage greater than the first voltage is applied to a word line of the selection transistor. A current passing through the EEPROM cell is compared with a predetermined reference current to read the data stored in the EEPROM cell. An on-cell current of the EEPROM cell may be increased in an erased state and the data in the cell may be readily discriminated.

摘要翻译： 在EEPROM单元中读取数据的方法中，用于读取的位线电压被施加到包括存储晶体管和选择晶体管的EEPROM单元。 第一电压被施加到存储晶体管的感测线。 大于第一电压的第二电压被施加到选择晶体管的字线。 将通过EEPROM单元的电流与预定的参考电流进行比较，以读取存储在EEPROM单元中的数据。 可以在擦除状态下增加EEPROM单元的通电池电流，并且可以容易地区分单元中的数据。

公开(公告)号：US07638387B2

公开(公告)日：2009-12-29

申请号：US11823381

申请日：2007-06-27

申请人： Yong-Kyu Lee ,  Hee-Seog Jeon ,  Jeong-Uk Han ,  Young-Ho Kim ,  Myung-Jo Chun

发明人： Yong-Kyu Lee ,  Hee-Seog Jeon ,  Jeong-Uk Han ,  Young-Ho Kim ,  Myung-Jo Chun

IPC分类号： H01L21/8234

CPC分类号： H01L27/1021

摘要： A mask read-only memory (ROM) includes a dielectric layer formed on a substrate and a plurality of first conductive lines formed on the dielectric layer. A plurality of diodes are formed in the first conductive lines, and a plurality of final vias are formed for a first set of the diodes each representing a first type of memory cell, with no final via being formed for a second set of diodes each representing a second type of memory cell. Each of a plurality of second conductive lines is formed over a column of the diodes.

摘要翻译： 掩模只读存储器（ROM）包括形成在基板上的电介质层和形成在电介质层上的多个第一导电线。 在第一导线中形成多个二极管，并且为第一组二极管形成多个最终通孔，每个二极管表示第一类型的存储单元，没有形成用于第二组二极管的最终通孔，每个二极管表示 第二种类型的存储单元。 多个第二导电线中的每一个形成在二极管的列上。

公开(公告)号：US07602008B2

公开(公告)日：2009-10-13

申请号：US11957037

申请日：2007-12-14

申请人： Sung-Taeg Kang ,  Hyok-Ki Kwon ,  Bo Young Seo ,  Seung Beom Yoon ,  Hee Seog Jeon ,  Yong-Suk Choi ,  Jeong-Uk Han

发明人： Sung-Taeg Kang ,  Hyok-Ki Kwon ,  Bo Young Seo ,  Seung Beom Yoon ,  Hee Seog Jeon ,  Yong-Suk Choi ,  Jeong-Uk Han

IPC分类号： H01L27/115

CPC分类号： H01L29/7887 ,  H01L29/66825

摘要： Non-volatile memory devices and methods for fabricating non-volatile memory devices are disclosed. More specifically, split gate memory devices are provided having frameworks that provide increased floating gate coupling ratios, thereby enabling enhanced programming and erasing efficiency and performance.

摘要翻译： 公开了用于制造非易失性存储器件的非易失性存储器件和方法。 更具体地，提供具有提供增加的浮栅耦合比的框架的分割门存储器件，从而实现增强的编程和擦除效率和性能。

公开(公告)号：US07531410B2

公开(公告)日：2009-05-12

申请号：US11648057

申请日：2006-12-29

申请人： Yong-Suk Choi ,  Jeong-Uk Han ,  Hee-Seog Jeon ,  Seung-Jin Yang ,  Hyok-Ki Kwon

发明人： Yong-Suk Choi ,  Jeong-Uk Han ,  Hee-Seog Jeon ,  Seung-Jin Yang ,  Hyok-Ki Kwon

IPC分类号： H01L21/336

CPC分类号： H01L29/7881 ,  H01L21/28273 ,  H01L29/42336

摘要： A semiconductor flash memory device. The flash memory device includes a floating gate electrode disposed in a recess having slanted sides in a semiconductor substrate. A gate insulation film is interposed between the floating gate electrode and the semiconductor substrate. A control gate electrode is disposed over the floating gate electrode. The floating gate electrode includes projections adjacent to the slanted sides of the recess.

摘要翻译： 半导体闪存器件。 闪存器件包括设置在具有在半导体衬底中的倾斜侧面的凹部中的浮栅电极。 栅极绝缘膜介于浮栅电极和半导体衬底之间。 控制栅电极设置在浮栅电极上。 浮栅电极包括与凹部的倾斜侧相邻的突起。

公开(公告)号：US07514739B2

公开(公告)日：2009-04-07

申请号：US11687942

申请日：2007-03-19

申请人： Young-Sam Park ,  Seung-Beom Yoon ,  Jeong-Uk Han ,  Sung-Taeg Kang ,  Seung-Jin Yang

发明人： Young-Sam Park ,  Seung-Beom Yoon ,  Jeong-Uk Han ,  Sung-Taeg Kang ,  Seung-Jin Yang

IPC分类号： H01L29/76 ,  H01L29/788

CPC分类号： H01L29/7854 ,  H01L21/28273 ,  H01L29/42324 ,  H01L29/66553 ,  H01L29/66795 ,  H01L29/7851 ,  H01L29/7853 ,  H01L29/7881

摘要： A stack-type nonvolatile semiconductor device comprises a memory device formed on a substrate including a semiconductor body elongated in one direction, having a cross section perpendicular to a main surface, having a predetermined curvature, a channel region on the semiconductor body along the circumference, a tunneling insulating layer on the channel region, a floating gate on the tunneling insulating layer, insulated from the channel region, a high dielectric constant material layer on the floating gate, a metallic control gate on the high dielectric constant material layer, insulated from the floating gate, and source and drain regions adjacent to the metallic control gate on the semiconductor body, an inter-insulating layer on the memory device, and a conductive layer on the inter-insulating layer, and a memory device formed on the conductive layer including, a semiconductor body elongated in one direction having a cross section perpendicular to a main surface, having a predetermined curvature, a channel region along the circumference of the semiconductor body, a tunneling insulating layer on the channel region, a floating gate on the tunneling insulating layer, electrically insulated from the channel region, a high dielectric constant material layer on the floating gate, a metallic control gate on the high dielectric constant material layer, insulated from the floating gate, and source and drain regions adjacent to the metallic control gate.

摘要翻译： 堆叠型非易失性半导体器件包括：形成在基板上的存储器件，该存储器件包括在一个方向上延伸的半导体本体，具有垂直于主表面的横截面，具有预定曲率，半导体本体上沿着圆周的沟道区域， 沟道区域上的隧道绝缘层，与沟道区绝缘的隧道绝缘层上的浮动栅极，浮置栅极上的高介电常数材料层，高介电常数材料层上的金属控制栅极，绝缘层 浮置栅极，与半导体主体上的金属控制栅极相邻的源极和漏极区域，存储器件上的绝缘层和绝缘层上的导电层，以及形成在导电层上的存储器件，包括 具有垂直于主表面的横截面在一个方向上延伸的半导体本体，具有预制件 沿着半导体本体的圆周的通道区域，沟道区域上的隧道绝缘层，隧道绝缘层上的浮动栅极，与沟道区电绝缘，浮置栅极上的高介电常数材料层， 在高介电常数材料层上的金属控制栅极，与浮动栅极绝缘，以及与金属控制栅极相邻的源极和漏极区域。

公开(公告)号：US20070164344A1

公开(公告)日：2007-07-19

申请号：US11687942

申请日：2007-03-19

申请人： Young-Sam Park ,  Seung-Beom Yoon ,  Jeong-Uk Han ,  Sung-Taeg Kang ,  Seung-Jin Yang

发明人： Young-Sam Park ,  Seung-Beom Yoon ,  Jeong-Uk Han ,  Sung-Taeg Kang ,  Seung-Jin Yang

IPC分类号： H01L29/76

CPC分类号： H01L29/7854 ,  H01L21/28273 ,  H01L29/42324 ,  H01L29/66553 ,  H01L29/66795 ,  H01L29/7851 ,  H01L29/7853 ,  H01L29/7881

摘要： A stack-type nonvolatile semiconductor device comprises a memory device formed on a substrate including a semiconductor body elongated in one direction, having a cross section perpendicular to a main surface, having a predetermined curvature, a channel region on the semiconductor body along the circumference, a tunneling insulating layer on the channel region, a floating gate on the tunneling insulating layer, insulated from the channel region, a high dielectric constant material layer on the floating gate, a metallic control gate on the high dielectric constant material layer, insulated from the floating gate, and source and drain regions adjacent to the metallic control gate on the semiconductor body, an inter-insulating layer on the memory device, and a conductive layer on the inter-insulating layer, and a memory device formed on the conductive layer including, a semiconductor body elongated in one direction having a cross section perpendicular to a main surface, having a predetermined curvature, a channel region along the circumference of the semiconductor body, a tunneling insulating layer on the channel region, a floating gate on the tunneling insulating layer, electrically insulated from the channel region, a high dielectric constant material layer on the floating gate, a metallic control gate on the high dielectric constant material layer, insulated from the floating gate, and source and drain regions adjacent to the metallic control gate.

摘要翻译： 堆叠型非易失性半导体器件包括：形成在基板上的存储器件，该存储器件包括在一个方向上延伸的半导体本体，具有垂直于主表面的横截面，具有预定曲率，半导体本体上沿着圆周的沟道区域， 沟道区域上的隧道绝缘层，与沟道区绝缘的隧道绝缘层上的浮动栅极，浮置栅极上的高介电常数材料层，高介电常数材料层上的金属控制栅极，绝缘层 浮置栅极，与半导体主体上的金属控制栅极相邻的源极和漏极区域，存储器件上的绝缘层和绝缘层上的导电层，以及形成在导电层上的存储器件，包括 具有垂直于主表面的横截面在一个方向上延伸的半导体本体，具有预制件 沿着半导体本体的圆周的通道区域，沟道区域上的隧道绝缘层，隧道绝缘层上的浮动栅极，与沟道区电绝缘，浮置栅极上的高介电常数材料层， 在高介电常数材料层上的金属控制栅极，与浮动栅极绝缘，以及与金属控制栅极相邻的源极和漏极区域。

公开(公告)号：US20060008984A1

公开(公告)日：2006-01-12

申请号：US11138702

申请日：2005-05-26

申请人： Hee-Seog Jeon ,  Seung-Beom Yoon ,  Jeong-Uk Han ,  Yong-Tae Kim

发明人： Hee-Seog Jeon ,  Seung-Beom Yoon ,  Jeong-Uk Han ,  Yong-Tae Kim

IPC分类号： H01L21/336

CPC分类号： H01L27/11521 ,  H01L27/115 ,  H01L29/7885

摘要： A method of forming a split-gate non-volatile memory cell can include forming first and second adjacent floating gates self-aligned to a field oxide region therebetween. An oxide layer is formed covering the first and second adjacent floating gates and the field oxide region, the oxide layer electrically isolates the first and second adjacent floating gates from one another. A control gate is formed on the oxide layer on the first and second adjacent floating gates. Related devices are also disclosed.

摘要翻译： 形成分闸非易失性存储单元的方法可以包括形成与其之间的场氧化物区域自对准的第一和第二相邻浮置栅极。 形成覆盖第一和第二相邻浮动栅极和场氧化物区域的氧化物层，氧化物层将第一和第二相邻浮栅彼此电隔离。 控制栅极形成在第一和第二相邻浮动栅极上的氧化物层上。 还公开了相关设备。

公开(公告)号：US08362545B2

公开(公告)日：2013-01-29

申请号：US13064344

申请日：2011-03-21

申请人： Tea-Kwang Yu ,  Jeong-Uk Han ,  Yong-Tae Kim

发明人： Tea-Kwang Yu ,  Jeong-Uk Han ,  Yong-Tae Kim

IPC分类号： H01L29/788

CPC分类号： H01L27/11521 ,  H01L27/11519 ,  H01L27/11524

摘要： The nonvolatile memory device includes a semiconductor substrate, and a device isolation layer defining an active region in the semiconductor substrate. The device isolation layer includes a top surface lower than a top surface of the semiconductor substrate, such that a side-upper surface of the active region is exposed. A sense line crosses both the active region and the device isolation layer, and a word line, spaced apart from the sense line, crosses both the active region and the device isolation layer.