Self-aligned dual damascene arrangement for metal interconnection with
low k dielectric constant materials and nitride middle etch stop layer
    31.
    发明授权
    Self-aligned dual damascene arrangement for metal interconnection with low k dielectric constant materials and nitride middle etch stop layer 有权
    用于与低k介电常数材料和氮化物中间蚀刻停止层的金属互连的自对准双镶嵌布置

    公开(公告)号:US6153514A

    公开(公告)日:2000-11-28

    申请号:US225215

    申请日:1999-01-04

    摘要: A method of forming a self-aligned dual damascene structure in a semiconductor device arrangement forms a first low k dielectric material over an underlying metal interconnect layer, such as a copper interconnect layer. A nitride etch stop layer is formed on the first low k dielectric layer, and a second low k dielectric layer is formed on the nitride etch stop layer. A trench is etched into the second low k dielectric layer, followed by the etching of a via into the first low k dielectric layer. The first and second low k dielectric materials are different from one another so that they have different sensitivity to at least one etchant chemistry. Undercutting in the second dielectric layer caused by overetching is thereby prevented during the etching of the via in the second dielectric layer by employing an etch chemistry that etches only the first low k dielectric material and not the second low k dielectric material.

    摘要翻译: 在半导体器件布置中形成自对准双镶嵌结构的方法在下面的金属互连层(例如铜互连层)上形成第一低k电介质材料。 在第一低k电介质层上形成氮化物蚀刻停止层,在氮化物蚀刻停止层上形成第二低k电介质层。 将沟槽蚀刻到第二低k介电层中,随后将通孔蚀刻到第一低k电介质层中。 第一和第二低k电介质材料彼此不同,使得它们对至少一种蚀刻剂化学物质具有不同的灵敏度。 因此,在蚀刻第二介质层中的通孔时,通过采用蚀刻仅仅第一低k电介质材料而不是第二低k电介质材料的蚀刻化学法,由此防止了由过蚀刻引起的第二电介质层中的底切。

    Method for construction and fabrication of submicron field-effect
transistors by optimization of poly oxide process
    32.
    发明授权
    Method for construction and fabrication of submicron field-effect transistors by optimization of poly oxide process 失效
    通过优化多晶氧化物工艺构建和制造亚微米场效应晶体管的方法

    公开(公告)号:US5858844A

    公开(公告)日:1999-01-12

    申请号:US485871

    申请日:1995-06-07

    摘要: The present invention comprises an innovative gate oxidation process after the disposition of the gate and prior to the disposition of the source and the drain by exposing the gate to oxygen at a predetermined temperature and for a predetermined time period for the optimized transistor performance. During the innovative gate oxidation process, oxygen penetrates into the interfaces of the gate conductive layer gate oxide and the gate dielectric layer silicon substrate and oxidizes portions of the gate conductive layer at the interfaces due to the oxygen smiling or the bird beak effect, which results in an increased effective thickness of the gate dielectric layer. Optionally, HCl can be introduced at a predetermined flowrate during the innovative gate oxidation process. A particular embodiment of the present invention is the fabrication of MOS transistors with polysilicon as the gate conductive layer and silicon oxide as the gate dielectric layer, and with the source and drain fabricated by the low doped drain (LDD) implant. In this particular case, the innovative gate oxidation process is a polysilicon oxidation (POX) process grown before LDD implant. The oxidation temperature and oxidation time duration for optimized transistor performances have been found to be 850.degree. C. and 115 minutes, respectively. This present invention is utilized to achieve maximum speed and performance by optimizing the POX process.

    摘要翻译: 本发明包括在门的配置之后并且在通过在预定温度下将栅极暴露于氧气并在预定时间段内对于优化的晶体管性能进行设置之前的创新的栅极氧化工艺。 在创新的栅极氧化过程中,氧气渗透入栅极导电层栅极氧化物和栅极电介质层硅衬底的界面,并由于氧气微笑或鸟喙效应而在界面处氧化栅极导电层的部分,从而导致 在栅介电层的有效厚度增加。 任选地,可以在创新的栅极氧化过程期间以预定流量引入HCl。 本发明的一个具体实施例是制造具有多晶硅作为栅极导电层和氧化硅作为栅极介电层的MOS晶体管,并且通过低掺杂漏极(LDD)注入制造源极和漏极。 在这种特殊情况下,创新的栅极氧化工艺是在LDD植入之前生长的多晶硅氧化(POX)工艺。 已经发现优化的晶体管性能的氧化温度和氧化时间分别为850℃和115分钟。 本发明用于通过优化POX过程来实现最大速度和性能。