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31.发明申请SEMICONDUCTOR DEVICE AND INTEGRATED CIRCUIT WITH HIGH-K/METAL GATE WITHOUT HIGH-K DIRECT CONTACT WITH STI 审中-公开具有高K /金属栅的半导体器件和集成电路，与高K直接接触STI公开(公告)号：US20130146975A1
公开(公告)日：2013-06-13
申请号：US13316677
申请日：2011-12-12
IPC分类号： H01L27/088 , H01L21/762
CPC分类号： H01L29/66545 , H01L21/76224 , H01L21/823462 , H01L21/823481 , H01L29/7833
摘要： A method, semiconductor device, and integrated circuit with a high-k/metal gate without high-k direct contact with STI. A high-k dielectric and a pad film are deposited directly onto a semiconductor substrate. Shallow trench isolation is performed, with shallow trenches etched directly into the pad film, the high-k material, and the substrate. The shallow trench is lined with an oxygen diffusion barrier and is subsequently filled with an insulating dielectric material. Thereafter the pad film and the insulating dielectric are recessed to a point where the oxygen diffusion barrier still remains between the insulating dielectric and the high-k material, preventing any contact there between. Afterwards a conductive gate is formed overlying the device.
摘要翻译： 具有高k /金属栅极的方法，半导体器件和集成电路，无需与STI直接接触。 将高k电介质和焊盘膜直接沉积到半导体衬底上。 执行浅沟槽隔离，其中浅沟槽直接蚀刻到衬垫膜，高k材料和衬底中。 浅沟槽衬有氧扩散阻挡层，随后填充有绝缘介电材料。 此后，衬垫膜和绝缘电介质凹陷到氧扩散阻挡层仍然保留在绝缘电介质和高k材料之间的点，防止其间的任何接触。 之后形成覆盖该器件的导电栅极。
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32.发明申请Method and Structure For Forming On-Chip High Quality Capacitors With ETSOI Transistors 有权用ETSOI晶体管形成片上高品质电容器的方法和结构公开(公告)号：US20130146959A1
公开(公告)日：2013-06-13
申请号：US13316635
申请日：2011-12-12
申请人： Kangguo Cheng , Bruce Doris , Ali Khakifirooz , Ghavam Shahidi
发明人： Kangguo Cheng , Bruce Doris , Ali Khakifirooz , Ghavam Shahidi
CPC分类号： H01L27/1203 , H01L27/0629 , H01L27/105 , H01L27/10805 , H01L28/40 , H01L29/66181 , H01L29/94
摘要： An ETSOI transistor and a capacitor are formed respectively in a transistor and capacitor region thereof by etching through an ETSOI and thin BOX layers in a replacement gate HK/MG flow. The capacitor formation is compatible with an ETSOI replacement gate CMOS flow. A low resistance capacitor electrode makes it possible to obtain a high quality capacitor or varactor. The lack of topography during dummy gate patterning are achieved by lithography in combination accompanied with appropriate etch.
摘要翻译： 通过在替换栅极HK / MG流中通过ETSOI和薄BOX层蚀刻，分别在其晶体管和电容器区域中形成ETSOI晶体管和电容器。 电容器形成与ETSOI替代栅极CMOS流相兼容。 低电阻电容器电极可以获得高质量的电容器或变容二极管。 虚拟栅极图案化期间缺乏形貌通过光刻结合并伴随着适当的蚀刻来实现。
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公开(公告)号：US20130146952A1
公开(公告)日：2013-06-13
申请号：US13314238
申请日：2011-12-08
IPC分类号： H01L27/088 , H01L21/336 , H01L21/02
CPC分类号： H01L27/1203 , H01L27/0629 , H01L29/94
摘要： A device including a semiconductor on insulator (SOI) substrate including a semiconductor device region and a capacitor device region. A semiconductor device present in the semiconductor device region. The semiconductor device including a gate structure present on a semiconductor on insulator (SOI) layer of the SOI substrate, extension source and drain regions present in the SOI layer on opposing sides of the gate structure, and raised source and drain regions composed of a first portion of an epitaxial semiconductor material on the SOI layer. A capacitor is present in the capacitor device region, said capacitor including a first electrode comprised of a second portion of the epitaxial semiconductor material that has a same composition and crystal structure as the first portion of the epitaxial semiconductor material, a node dielectric layer present on the second portion of the epitaxial semiconductor material, and a second electrode comprised of a conductive material.
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公开(公告)号：US08455932B2
公开(公告)日：2013-06-04
申请号：US13102073
申请日：2011-05-06
申请人： Ali Khakifirooz , Kangguo Cheng , Bruce B. Doris , Wilfried E. Haensch , Balasubramanian S. Haran , Pranita Kulkarni
发明人： Ali Khakifirooz , Kangguo Cheng , Bruce B. Doris , Wilfried E. Haensch , Balasubramanian S. Haran , Pranita Kulkarni
IPC分类号： H01L21/336
CPC分类号： H01L27/0207 , H01L21/28518 , H01L21/76802 , H01L21/76895 , H01L21/76897 , H01L21/823425 , H01L21/823437 , H01L21/823475 , H01L27/1104 , H01L29/41783 , H01L29/66545 , H01L29/6659 , H01L29/7834
摘要： A common cut mask is employed to define a gate pattern and a local interconnect pattern so that local interconnect structures and gate structures are formed with zero overlay variation relative to one another. A local interconnect structure may be laterally spaced from a gate structure in a first horizontal direction, and contact another gate structure in a second horizontal direction that is different from the first horizontal direction. Further, a gate structure may be formed to be collinear with a local interconnect structure that adjoins the gate structure. The local interconnect structures and the gate structures are formed by a common damascene processing step so that the top surfaces of the gate structures and the local interconnect structures are coplanar with each other.
摘要翻译： 采用公共切割掩模来限定栅极图案和局部互连图案，使得局部互连结构和栅极结构相对于彼此形成为零覆盖变化。 局部互连结构可以在第一水平方向上与栅极结构横向间隔开，并且在与第一水平方向不同的第二水平方向上接触另一个栅极结构。 此外，栅极结构可以形成为与邻接栅极结构的局部互连结构共线。 局部互连结构和栅极结构通过公共镶嵌处理步骤形成，使得栅极结构的顶表面和局部互连结构彼此共面。
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公开(公告)号：US20130082311A1
公开(公告)日：2013-04-04
申请号：US13609747
申请日：2012-09-11
IPC分类号： H01L29/78
CPC分类号： H01L29/4983 , H01L29/49 , H01L29/51 , H01L29/66545 , H01L29/66553 , H01L29/66628 , H01L29/66636 , H01L29/66772 , H01L29/7834
摘要： Transistor devices and methods of their fabrication are disclosed. In one method, a dummy gate structure is formed on a substrate. Bottom portions of the dummy gate structure are undercut. In addition, stair-shaped, raised source and drain regions are formed on the substrate and within at least one undercut formed by the undercutting. The dummy gate structure is removed and a replacement gate is formed on the substrate.
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公开(公告)号：US08404540B2
公开(公告)日：2013-03-26
申请号：US13446602
申请日：2012-04-13
IPC分类号： H01L21/8238
CPC分类号： H01L29/66628 , H01L21/26513 , H01L29/0847 , H01L29/41783 , H01L29/665 , H01L29/6656 , H01L29/6659 , H01L29/7834
摘要： A device and method for reducing junction leakage in a semiconductor junction includes forming a faceted raised structure in a source/drain region of the device. Dopants are diffused from the faceted raised structure into a substrate below the faceted raised structure to form source/drain regions. A sprinkle implantation is applied on the faceted raised structure to produce a multi-depth dopant profile in the substrate for the source/drain regions.
摘要翻译： 用于减少半导体结中的结漏电的器件和方法包括在器件的源极/漏极区域中形成刻面的凸起结构。 掺杂剂从小面凸起结构扩散到小平面凸起结构下面的基底中以形成源极/漏极区域。 在刻面凸起结构上施加喷洒注入，以在源/漏区的衬底中产生多深度掺杂物分布。
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公开(公告)号：US20130062704A1
公开(公告)日：2013-03-14
申请号：US13472680
申请日：2012-05-16
IPC分类号： H01L27/092
CPC分类号： H01L29/51 , H01L21/28176 , H01L21/823857 , H01L21/823864 , H01L29/49 , H01L29/66545 , H01L29/66553 , H01L29/66606 , H01L29/7833
摘要： A complementary metal oxide semiconductor (CMOS) structure having multiple threshold voltage devices includes a first transistor device and a second transistor device formed on a semiconductor substrate. A set of vertical oxide spacers selectively formed for the first transistor device are in direct contact with a gate dielectric layer of the first transistor device such that the first transistor device has a shifted threshold voltage with respect to the second transistor device.
摘要翻译： 具有多个阈值电压器件的互补金属氧化物半导体（CMOS）结构包括形成在半导体衬底上的第一晶体管器件和第二晶体管器件。 为第一晶体管器件选择性地形成的一组垂直氧化物间隔物与第一晶体管器件的栅介质层直接接触，使得第一晶体管器件相对于第二晶体管器件具有偏移的阈值电压。
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38.发明授权Thin channel device and fabrication method with a reverse embedded stressor 有权具有反向嵌入式应力源的薄通道器件和制造方法公开(公告)号：US08383474B2
公开(公告)日：2013-02-26
申请号：US12789699
申请日：2010-05-28
IPC分类号： H01L21/8238
CPC分类号： H01L29/7849 , H01L21/26506 , H01L29/66772 , H01L29/785 , H01L29/78654
摘要： A device and method for inducing stress in a semiconductor layer includes providing a substrate having a dielectric layer formed between a first semiconductor layer and a second semiconductor layer. A removable buried layer is provided on or in the second semiconductor layer. A gate structure with side spacers is formed on the first semiconductor layer. Recesses are formed down to the removable buried layer in areas for source and drain regions. The removable buried layer is etched away to form an undercut below the dielectric layer below the gate structure. A stressor layer is formed in the undercut, and source and drain regions are formed.
摘要翻译： 用于在半导体层中诱发应力的装置和方法包括提供在第一半导体层和第二半导体层之间形成介电层的基板。 可移除的掩埋层设置在第二半导体层上或第二半导体层中。 在第一半导体层上形成具有侧面间隔物的栅极结构。 在源区和漏区的区域中形成凹陷到可移除的掩埋层。 蚀刻掉可移除的掩埋层，以在栅极结构下面的介电层下方形成底切。 在底切中形成应力层，形成源区和漏区。
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公开(公告)号：US20130032876A1
公开(公告)日：2013-02-07
申请号：US13195153
申请日：2011-08-01
IPC分类号： H01L27/088 , H01L21/336 , H01L29/78
CPC分类号： H01L29/66545 , H01L29/66628 , H01L29/66772 , H01L29/66795
摘要： A transistor structure includes a channel disposed between a source and a drain; a gate conductor disposed over the channel and between the source and the drain; and a gate dielectric layer disposed between the gate conductor and the source, the drain and the channel. In the transistor structure a lower portion of the source and a lower portion of the drain that are adjacent to the channel are disposed beneath and in contact with the gate dielectric layer to define a sharply defined source-drain extension region. Also disclosed is a replacement gate method to fabricate the transistor structure.
摘要翻译： 晶体管结构包括设置在源极和漏极之间的沟道; 设置在所述通道上并且在所述源极和所述漏极之间的栅极导体; 以及设置在栅极导体和源极之间的栅介质层，漏极和沟道。 在晶体管结构中，源极的下部和与沟道相邻的漏极的下部设置在栅极介电层的下方并与栅极介电层接触以限定明确限定的源 - 漏扩展区。 还公开了制造晶体管结构的替代栅极方法。
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公开(公告)号：US08278175B2
公开(公告)日：2012-10-02
申请号：US12813311
申请日：2010-06-10
IPC分类号： H01L21/335
CPC分类号： H01L21/823431 , H01L21/823412 , H01L21/823807 , H01L21/823821 , H01L29/66795 , H01L29/7843 , H01L29/7846 , H01L29/785
摘要： Methods for fabricating FET device structures are disclosed. The methods include receiving a fin of a Si based material, and converting a region of the fin into an oxide element. The oxide element exerts pressure onto the fin where a Fin-FET device is fabricated. The exerted pressure induces compressive stress in the device channel of the Fin-FET device. The methods also include receiving a rectangular member of a Si based material and converting a region of the member into an oxide element. The methods further include patterning the member that N fins are formed in parallel, while being abutted by the oxide element, which exerts pressure onto the N fins. Fin-FET devices are fabricated in the compressed fins, which results in compressively stressed device channels. FET devices structures are also disclosed. An FET devices structure has a Fin-FET device with a fin of a Si based material. An oxide element is abutting the fin and exerts pressure onto the fin. The Fin-FET device channel is compressively stressed due to the pressure on the fin. A further FET device structure has Fin-FET devices in a row each having fins. An oxide element extending perpendicularly to the row of fins is abutting the fins and exerts pressure onto the fins. Device channels of the Fin-FET devices are compressively stressed due to the pressure on the fins.
摘要翻译： 公开了用于制造FET器件结构的方法。 所述方法包括接收Si基材料的翅片，以及将鳍片的区域转换为氧化物元件。 氧化物元件在制造Fin-FET器件的鳍片上施加压力。 施加的压力在Fin-FET器件的器件沟道中引起压应力。 所述方法还包括接收Si基材料的矩形构件并将所述构件的区域转换为氧化物元件。 所述方法进一步包括在与N个翅片施加压力的同时被N型翅片平行地形成的构件图案化。 Fin-FET器件制造在压缩鳍片中，这导致压缩应力器件通道。 还公开了FET器件结构。 FET器件结构具有具有Si基材料的翅片的Fin-FET器件。 氧化物元件邻接翅片并对翅片施加压力。 Fin-FET器件通道由于鳍上的压力而受到压缩应力。 另外的FET器件结构具有各自具有鳍片的Fin-FET器件。 垂直于翅片排延伸的氧化物元件邻接散热片并对翅片施加压力。 Fin-FET器件的器件通道由于鳍片上的压力而受到压缩应力。
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