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    Tunnel field effect transistor
    3.
    发明授权
    Tunnel field effect transistor 有权
    隧道场效应晶体管

    公开(公告)号：US08318568B2

    公开(公告)日：2012-11-27

    申请号：US12760287

    申请日：2010-04-14

    申请人： Bruce B. Doris ,  Kangguo Cheng ,  Wilfried E. Haensch ,  Ali Khakifirooz ,  Isaac Lauer ,  Ghavam G. Shahidi

    发明人： Bruce B. Doris ,  Kangguo Cheng ,  Wilfried E. Haensch ,  Ali Khakifirooz ,  Isaac Lauer ,  Ghavam G. Shahidi

    IPC分类号： H01L21/336

    CPC分类号： H01L21/26586 ,  H01L29/665 ,  H01L29/66636 ,  H01L29/66659 ,  H01L29/78

    摘要： A method for fabricating an FET device characterized as being a tunnel FET (TFET) device is disclosed. The method includes processing a gate-stack, and processing the adjoining source and drain junctions, which are of a first conductivity type. A hardmask is formed covering the gate-stack and the junctions. A tilted angle ion implantation is performed which is received by a first portion of the hardmask, and it is not received by a second portion of the hardmask due to the shadowing of the gate-stack. The implanted portion of the hardmask is removed and one of the junctions is exposed. The junction is etched away, and a new junction, typically in-situ doped to a second conductivity type, is epitaxially grown into its place. A device characterized as being an asymmetrical TFET is also disclosed. The source and drain junctions of the TFET are of different conductivity types, and the TFET also includes spacer formations in a manner that the spacer formation on one side of the gate-stack is thinner than on the other side of the gate-stack.

    摘要翻译： 公开了一种用于制造FET器件的方法，其特征在于是隧道FET（TFET）器件。 该方法包括处理栅极堆叠，以及处理第一导电类型的邻接的源极和漏极结。 形成覆盖栅极堆叠和结的硬掩模。 执行由硬掩模的第一部分接收的倾斜角度离子注入，并且由于栅极堆叠的阴影而不被硬掩模的第二部分接收。 去除硬掩模的注入部分，并露出其中一个接头。 该结被蚀刻掉，并且通常原位掺杂到第二导电类型的新结，外延生长到其位置。 还公开了一种特征为不对称TFET的器件。 TFET的源极和漏极结具有不同的导电类型，并且TFET还包括间隔物结构，使得栅极堆叠的一侧上的间隔物形成比栅极堆叠的另一侧更薄。

    TUNNEL FIELD EFFECT TRANSISTOR
    6.
    发明申请
    TUNNEL FIELD EFFECT TRANSISTOR 有权
    隧道场效应晶体管

    公开(公告)号：US20110254080A1

    公开(公告)日：2011-10-20

    申请号：US12760287

    申请日：2010-04-14

    申请人： Bruce B. Doris ,  Kangguo Cheng ,  Wilfried E. Haensch ,  Ali Khakifirooz ,  Isaac Lauer ,  Ghavam G. Shahidi

    发明人： Bruce B. Doris ,  Kangguo Cheng ,  Wilfried E. Haensch ,  Ali Khakifirooz ,  Isaac Lauer ,  Ghavam G. Shahidi

    IPC分类号： H01L29/78 ,  H01L21/336

    CPC分类号： H01L21/26586 ,  H01L29/665 ,  H01L29/66636 ,  H01L29/66659 ,  H01L29/78

    摘要： A method for fabricating an FET device characterized as being a tunnel FET (TFET) device is disclosed. The method includes processing a gate-stack, and processing the adjoining source and drain junctions, which are of a first conductivity type. A hardmask is formed covering the gate-stack and the junctions. A tilted angle ion implantation is performed which is received by a first portion of the hardmask, and it is not received by a second portion of the hardmask due to the shadowing of the gate-stack. The implanted portion of the hardmask is removed and one of the junctions is exposed. The junction is etched away, and a new junction, typically in-situ doped to a second conductivity type, is epitaxially grown into its place. A device characterized as being an asymmetrical TFET is also disclosed. The source and drain junctions of the TFET are of different conductivity types, and the TFET also includes spacer formations in a manner that the spacer formation on one side of the gate-stack is thinner than on the other side of the gate-stack.

    摘要翻译： 公开了一种用于制造FET器件的方法，其特征在于是隧道FET（TFET）器件。 该方法包括处理栅极堆叠，以及处理第一导电类型的邻接的源极和漏极结。 形成覆盖栅极堆叠和结的硬掩模。 执行由硬掩模的第一部分接收的倾斜角度离子注入，并且由于栅极堆叠的阴影而不被硬掩模的第二部分接收。 去除硬掩模的注入部分，并露出其中一个接头。 该结被蚀刻掉，并且通常原位掺杂到第二导电类型的新结，外延生长到其位置。 还公开了一种特征为不对称TFET的器件。 TFET的源极和漏极结具有不同的导电类型，并且TFET还包括间隔物结构，使得栅极堆叠的一侧上的间隔物形成比栅极堆叠的另一侧更薄。

    FinFET-compatible metal-insulator-metal capacitor
    7.
    发明授权
    FinFET-compatible metal-insulator-metal capacitor 有权
    FinFET兼容金属 - 绝缘体 - 金属电容器

    公开(公告)号：US08860107B2

    公开(公告)日：2014-10-14

    申请号：US12793292

    申请日：2010-06-03

    申请人： Wilfried E. Haensch ,  Pranita Kulkarni ,  Tenko Yamashita

    发明人： Wilfried E. Haensch ,  Pranita Kulkarni ,  Tenko Yamashita

    IPC分类号： H01L27/108 ,  H01L21/8234 ,  H01L27/08 ,  H01L27/06

    CPC分类号： H01L21/823431 ,  H01L27/0629 ,  H01L27/0805

    摘要： At least one semiconductor fin for a capacitor is formed concurrently with other semiconductor fins for field effect transistors. A lower conductive layer is deposited and lithographically patterned to form a lower conductive plate located on the at least one semiconductor fin. A dielectric layer and at least one upper conductive layer are formed and lithographically patterned to form a node dielectric and an upper conductive plate over the lower conductive plate as well as a gate dielectric and a gate conductor over the other semiconductor fins. The lower conductive plate, the node dielectric, and the upper conductive plate collectively form a capacitor. The finFETs may be dual gate finFETs or trigate finFETs. A buried insulator layer may be optionally recessed to increase the capacitance. Alternately, the lower conductive plate may be formed on a planar surface of the buried insulator layer.

    摘要翻译： 用于电容器的至少一个半导体鳍片与用于场效应晶体管的其它半导体鳍片同时形成。 沉积下导电层并以光刻方式图案化以形成位于至少一个半导体鳍片上的下导电板。 形成电介质层和至少一个上导电层，并将其光刻图案化以在下导电板上形成节点电介质和上导电板，以及在其它半导体鳍片上的栅极电介质和栅极导体。 下导电板，节点电介质和上导电板共同形成电容器。 finFET可以是双栅极finFET或者触发的finFET。 埋入的绝缘体层可以任选地凹入以增加电容。 或者，下导电板可以形成在掩埋绝缘体层的平坦表面上。

    Structure and Method to Fabricate Resistor on FinFET Processes
    8.
    发明申请
    Structure and Method to Fabricate Resistor on FinFET Processes 有权
    在FinFET工艺上制造电阻的结构和方法

    公开(公告)号：US20120175749A1

    公开(公告)日：2012-07-12

    申请号：US12985669

    申请日：2011-01-06

    申请人： Wilfried E. Haensch ,  Pranita Kulkarni ,  Tenko Yamashita

    发明人： Wilfried E. Haensch ,  Pranita Kulkarni ,  Tenko Yamashita

    IPC分类号： H01L29/06 ,  H01L21/22

    CPC分类号： H01L21/845 ,  H01L27/1211

    摘要： A structure comprises first and at least second fin structures are formed. Each of the first and at least second fin structures has a vertically oriented semiconductor body. The vertically oriented semiconductor body is comprised of vertical surfaces. A doped region in each of the first and at least second fin structures is comprised of a concentration of dopant ions present in the semiconductor body to form a first resistor and at least a second resistor, and a pair of merged fins formed on outer portions of the doped regions of the first and at least second fin structures. The pair of merged fins is electrically connected so that the first and at least second resistors are electrically connected in parallel with each other.

    摘要翻译： 一种结构包括形成第一和至少第二鳍结构。 第一鳍片结构和至少第二鳍片结构中的每一个具有垂直取向的半导体本体。 垂直取向的半导体主体由垂直表面组成。 第一和至少第二翅片结构中的每一个中的掺杂区域包括存在于半导体主体中的掺杂剂离子的浓度，以形成第一电阻器和至少第二电阻器，以及一对形成在 第一和至少第二鳍结构的掺杂区域。 这对合并的翅片电连接，使得第一和至少第二电阻器彼此并联电连接。

    Self-aligned contacts for field effect transistor devices
    10.
    发明授权
    Self-aligned contacts for field effect transistor devices 有权
    场效应晶体管器件的自对准触点

    公开(公告)号：US08367508B2

    公开(公告)日：2013-02-05

    申请号：US12757201

    申请日：2010-04-09

    申请人： Dechao Guo ,  Wilfried E. Haensch ,  Xinhui Wang ,  Keith Kwong Hon Wong

    发明人： Dechao Guo ,  Wilfried E. Haensch ,  Xinhui Wang ,  Keith Kwong Hon Wong

    IPC分类号： H01L21/336

    CPC分类号： H01L29/665 ,  H01L21/28088 ,  H01L21/28114 ,  H01L21/28525 ,  H01L21/76897 ,  H01L21/78 ,  H01L29/66545

    摘要： A method for forming a field effect transistor includes forming a gate stack, a spacer adjacent to opposing sides of the gate stack, a silicide source region and a silicide drain region on opposing sides of the spacer, epitaxially growing silicon on the source region and the drain region; forming a liner layer on the gate stack and the spacer, removing a portion of the liner layer to expose a portion of the hardmask layer, removing the exposed portions of the hardmask layer to expose a silicon layer of the gate stack, removing exposed silicon to expose a portion of a metal layer of the gate stack, the source region, and the drain region; and depositing a conductive material on the metal layer of the gate stack, the silicide source region, and the silicide drain region.

    摘要翻译： 一种用于形成场效应晶体管的方法，包括：形成栅极叠层，与栅叠层的相对侧相邻的间隔物，在间隔物的相对侧上的硅化物源区和硅化物漏极区，在源区上外延生长硅， 漏区; 在栅极堆叠和间隔物上形成衬垫层，去除衬里层的一部分以露出硬掩模层的一部分，去除硬掩模层的暴露部分以暴露栅堆叠的硅层，将暴露的硅去除 暴露栅叠层，源极区和漏区的金属层的一部分; 以及在栅叠层，硅化物源区和硅化物漏极区的金属层上沉积导电材料。