公开(公告)号：US20160265835A1

公开(公告)日：2016-09-15

申请号：US15064699

申请日：2016-03-09

申请人： John Brothers

发明人： John Brothers

IPC分类号： F25D23/00 ,  A01N1/02 ,  F25D23/02 ,  F25D3/10 ,  F25D17/06

CPC分类号： A01N1/0252 ,  A01N1/0257 ,  F25D3/10 ,  F25D2317/0682

摘要： A cryogenic freezer having a housing defining an interior chamber. A first and second fan are positioned in the chamber and are spaced apart from each other. At least one motor is drivingly connected to the fans so that, upon activation of the motor, the fans circulate air through the interior chamber in the same direction.

摘要翻译： 一种低温冷冻机，其具有限定内部室的壳体。 第一和第二风扇位于腔室中并且彼此间隔开。 至少一个电动机驱动地连接到风扇，使得在电动机启动时，风扇以相同的方向循环通过内部室的空气。

公开(公告)号：US08736627B2

公开(公告)日：2014-05-27

申请号：US11612573

申请日：2006-12-19

申请人： John Brothers

发明人： John Brothers

IPC分类号： G06F15/167

CPC分类号： G06T1/60

摘要： Provided are methods and systems for reducing memory bandwidth usage in a common buffer, multiple FIFO computing environment. The multiple FIFO's are arranged in coordination with serial processing units, such as in a pipeline processing environment. The multiple FIFO's contain pointers to entry addresses in a common buffer. Each subsequent FIFO receives only pointers that correspond to data that has not been rejected by the corresponding processing unit. Rejected pointers are moved to a free list for reallocation to later data.

摘要翻译： 提供了用于减少公共缓冲器，多个FIFO计算环境中的存储器带宽使用的方法和系统。 多个FIFO与串行处理单元协调配置，例如在流水线处理环境中。 多个FIFO包含指向公共缓冲区中的入口地址的指针。 每个后续FIFO仅接收与未被相应处理单元拒绝的数据相对应的指针。 被拒绝的指针被移动到空闲列表，以重新分配给稍后的数据。

公开(公告)号：US20130166885A1

公开(公告)日：2013-06-27

申请号：US13531013

申请日：2012-06-22

申请人： Karthik Ramani ,  Stephen Presant ,  John Brothers

发明人： Karthik Ramani ,  Stephen Presant ,  John Brothers

IPC分类号： G01K3/00 ,  G06F9/30

CPC分类号： G06F9/4893 ,  G01K7/427 ,  G06F1/20 ,  Y02D10/24

摘要： When an instruction is executed on an integrated circuit (IC), an activity level and temperature are measured. A relationship between the activity level and temperature is determined, to estimate the temperature from the activity level. The activity level is monitored and is input to a scheduler, which estimates the IC temperature based on the activity level. The scheduler distributes work taking into account the temperature of various IC regions and may include distributing work to the IC region that has a lowest estimated temperature or relatively lower estimated temperature (e.g., lower than the average IC or IC region temperature). When the utilization level of one or more IC regions is high, the scheduler is configured to reduce the clock speed or the voltage of the one or more IC regions, or flag the regions as being unavailable for additional workload.

摘要翻译： 当在集成电路（IC）上执行指令时，测量活动电平和温度。 确定活动水平和温度之间的关系，从活动水平估算温度。 监视活动级别，并将其输入到调度程序中，该调度程序将根据活动级别估算IC温度。 调度器考虑各种IC区域的温度来分配工作，并且可以包括将工作分配到具有最低估计温度或相对较低估计温度（例如低于平均IC或IC区域温度）的IC区域。 当一个或多个IC区域的使用级别高时，调度器被配置为降低一个或多个IC区域的时钟速度或电压，或将该区域标记为不可用于额外的工作负载。

公开(公告)号：US20110050710A1

公开(公告)日：2011-03-03

申请号：US12616636

申请日：2009-11-11

申请人： Greg SADOWSKI ,  Konstantine Iourcha ,  John Brothers

发明人： Greg SADOWSKI ,  Konstantine Iourcha ,  John Brothers

IPC分类号： G06F15/16 ,  G06T1/00

CPC分类号： G06F9/3879 ,  G06F9/544

摘要： Disclosed herein is a graphics-processing unit (GPU) having an internal memory for general-purpose use and applications thereof. Such a GPU includes a first internal memory, an execution unit coupled to the first internal memory, and an interface configured to couple the first internal memory to a second internal memory of an other processing unit. The first internal memory may comprise a stacked dynamic random access memory (DRAM) or an embedded DRAM. The interface may be further configured to couple the first internal memory to a display device. The GPU may also include another interface configured to couple the first internal memory to a central processing unit. In addition, the GPU may be embodied in software and/or included in a computing system.

摘要翻译： 这里公开了具有用于通用目的的内部存储器和其应用的图形处理单元（GPU）。 这样的GPU包括第一内部存储器，耦合到第一内部存储器的执行单元和被配置为将第一内部存储器耦合到另一个处理单元的第二内部存储器的接口。 第一内部存储器可以包括堆叠的动态随机存取存储器（DRAM）或嵌入式DRAM。 接口可以被进一步配置成将第一内部存储器耦合到显示装置。 GPU还可以包括被配置为将第一内部存储器耦合到中央处理单元的另一接口。 此外，GPU可以体现在软件中和/或包括在计算系统中。

公开(公告)号：US07737983B2

公开(公告)日：2010-06-15

申请号：US11552693

申请日：2006-10-25

申请人： John Brothers ,  Timour Paltashev ,  Hsilin Huang ,  Boris Prokopenko ,  Qunfeng (Fred) Liao

发明人： John Brothers ,  Timour Paltashev ,  Hsilin Huang ,  Boris Prokopenko ,  Qunfeng (Fred) Liao

IPC分类号： G06F1/20 ,  G06T1/00

CPC分类号： G06F9/542 ,  G06F9/3879 ,  G06F9/485 ,  G06F9/526 ,  G06T1/20

摘要： A method for high level synchronization between an application and a graphics pipeline comprises receiving an application instruction in an input stream at a predetermined component, such as a command stream processor (CSP), as sent by a central processing unit. The CSP may have a first portion coupled to a next component in the graphics pipeline and a second portion coupled to a plurality of components of the graphics pipeline. A command associated with the application instruction may be forwarded from the first portion to the next component in the graphics pipeline or some other component coupled thereto. The command may be received and thereafter executed. A response may be communicated on a feedback path to the second portion of the CSP. Nonlimiting exemplary application instructions that may be received and executed by the CSP include check surface fault, trap, wait, signal, stall, flip, and trigger.

摘要翻译： 一种用于应用程序和图形流水线之间的高级别同步的方法包括：在由中央处理单元发送的诸如命令流处理器（CSP）的预定组件的输入流中接收应用程序指令。 CSP可以具有耦合到图形流水线中的下一个组件的第一部分和耦合到图形流水线的多个组件的第二部分。 与应用指令相关联的命令可以从第一部分转发到图形流水线中的下一个组件或与其耦合的一些其它组件。 该命令可以被接收并且此后被执行。 响应可以在反馈路径上传送到CSP的第二部分。 可以由CSP接收和执行的非限制性示例性应用指令包括检查表面故障，陷阱，等待，信号，失速，翻转和触发。

公开(公告)号：US07545381B2

公开(公告)日：2009-06-09

申请号：US11272356

申请日：2005-11-10

申请人： Hsilin Huang ,  Timour Paltashev ,  John Brothers

发明人： Hsilin Huang ,  Timour Paltashev ,  John Brothers

IPC分类号： G06T1/00 ,  G06F9/46 ,  G06T1/20

CPC分类号： G06T15/005 ,  G06F9/461 ,  G06T1/20

摘要： A graphics processing unit (“GPU”) is configured to receive an interrupt command from a CPU or internal interrupt event while the GPU is processing a first context. The GPU saves the first context to memory and records a precise processing position for the first context corresponding to the point interrupted. Thereafter, the GPU loads a second context to the processing portion of the GPU from memory and begins executing instructions associated with the second context. After the second context is complete of if an interrupt command directs restoration of the first context, the GPU's processor switches to the first context for continued processing. The first context is retrieved from memory and restored to the precise processing position where previously interrupted. The GPU then processes a remainder portion of the first context from the precise processing point to an end of the first context.

摘要翻译： 图形处理单元（“GPU”）被配置为在GPU处理第一上下文时从CPU或内部中断事件接收中断命令。 GPU将第一上下文保存到存储器，并记录与中断点相对应的第一上下文的精确处理位置。 此后，GPU从存储器将第二上下文加载到GPU的处理部分，并开始执行与第二上下文相关联的指令。 在第二个上下文完成之后，如果中断命令指示第一个上下文的恢复，则GPU的处理器切换到第一上下文以继续处理。 第一个上下文从存储器中检索并恢复到之前中断的精确处理位置。 然后，GPU处理从精确处理点到第一上下文结束的第一上下文的余数部分。

公开(公告)号：US20080094407A1

公开(公告)日：2008-04-24

申请号：US11765119

申请日：2007-06-19

申请人： Jim Xu ,  John Brothers ,  Sibyl Shao

发明人： Jim Xu ,  John Brothers ,  Sibyl Shao

IPC分类号： G06T11/40

CPC分类号： G06T15/04 ,  G06T1/60

摘要： Systems and methods for graphics data management are described. One embodiment includes a graphics processing system comprising a texture management unit configured to organize texture map data according to a slice major format, wherein the texture map data spans at least one mip level. Furthermore, the graphics processing system comprises a texture cache, wherein the texture cache is coupled to the texture management unit and configured to receive the reorganized texture map data from the texture management unit.

摘要翻译： 描述了用于图形数据管理的系统和方法。 一个实施例包括图形处理系统，其包括纹理管理单元，其被配置为根据切片主格式来组织纹理映射数据，其中纹理映射数据跨越至少一个mip级别。 此外，图形处理系统包括纹理缓存，其中纹理高速缓存耦合到纹理管理单元并且被配置为从纹理管理单元接收重组的纹理映射数据。

公开(公告)号：US20080010596A1

公开(公告)日：2008-01-10

申请号：US11763720

申请日：2007-06-15

申请人： Zahid Hussain ,  John Brothers ,  Jim Xu

发明人： Zahid Hussain ,  John Brothers ,  Jim Xu

IPC分类号： G06F3/00

CPC分类号： H04N19/436 ,  H04N19/12 ,  H04N19/44 ,  H04N19/61

摘要： Included are embodiments for processing video data. At least one embodiment includes a logic configured to receive video data having a format chosen from at least two formats and logic configured to receive an instruction from an instruction set including an indication of the format of the video data. Some embodiments include first parallel logic configured to process video data according to a first format in response to the indication is the first format and second parallel logic configured to process the video data according to a second format in response to the indication is the second format.

摘要翻译： 包括用于处理视频数据的实施例。 至少一个实施例包括被配置为接收具有从至少两种格式选择的格式的视频数据的逻辑，以及被配置为从包括视频数据的格式的指示的指令集接收指令的逻辑。 一些实施例包括被配置为响应于该指示来处理视频数据的第一并行逻辑，第一格式和第二并行逻辑被配置为根据第二格式来处理视频数据，响应于该指示是第二格式。

公开(公告)号：US20070115292A1

公开(公告)日：2007-05-24

申请号：US11552649

申请日：2006-10-25

申请人： John Brothers ,  Hsilin Huang ,  Boris Prokopenko

发明人： John Brothers ,  Hsilin Huang ,  Boris Prokopenko

IPC分类号： G06T1/20

CPC分类号： G06F9/542 ,  G06F9/3879 ,  G06F9/485 ,  G06F9/526 ,  G06T1/20

摘要： A GPU pipeline is synchronized by sending a fence command from a first module to an addressed synchronization register pair. Fence command associated data may be stored in a fence register of the addressed register pair. A second module sends a wait command with associated data to the addressed register pair, which may be compared to the data in the fence register. If the fence register data is greater than or equal to the wait command associated data, the second module may be acknowledged for sending the wait command and released for processing other graphics operations. If the fence register data is less than the wait command associated data, the second module is stalled until subsequent receipt of a fence command having data that is greater than or equal to the wait command associated data, which may be written to a wait register associated to the addressed register pair.

摘要翻译： 通过从第一模块发送fence命令到寻址的同步寄存器对来同步GPU流水线。 栅栏命令相关数据可以存储在寻址的寄存器对的栅栏寄存器中。 第二个模块发送一个具有关联数据的等待命令到寻址的寄存器对，这可以与围栏寄存器中的数据进行比较。 如果栅栏寄存器数据大于等于等待命令关联数据，则可以确认第二模块用于发送等待命令并被释放用于处理其他图形操作。 如果栅栏寄存器数据小于等待命令相关联的数据，则第二模块停止，直到后续接收到具有大于或等于等待命令关联数据的数据的围栏命令，该等待命令可被写入等待寄存器 到寻址寄存器对。

公开(公告)号：US07030878B2

公开(公告)日：2006-04-18

申请号：US10804862

申请日：2004-03-19

申请人： Jiangming Xu ,  Wen-Chung Chen ,  Yuanfeng Wang ,  Liang Li ,  John Brothers ,  Boris Prokopenko

发明人： Jiangming Xu ,  Wen-Chung Chen ,  Yuanfeng Wang ,  Liang Li ,  John Brothers ,  Boris Prokopenko

IPC分类号： G06T15/40 ,  G06T9/00 ,  G06F13/00

CPC分类号： G06T15/60 ,  G06T15/005

摘要： The computer graphics system is configured to generate a shadow effect with a stencil shadow volume method using a combination of compressed and uncompressed stencil buffers in coordination with compressed and uncompressed depth data buffers. An uncompressed stencil buffer is capable of storing stencil shadow volume data for each pixel and a compressed stencil buffer is capable of storing stencil shadow volume data for a group of pixels.

摘要翻译： 计算机图形系统被配置为使用压缩和未压缩模板缓冲器的组合，使用压缩和未压缩的深度数据缓冲器来生成具有模板阴影卷方法的阴影效果。 未压缩的模板缓冲器能够存储每个像素的模板阴影体积数据，并且压缩模板缓冲器能够存储一组像素的模板阴影体积数据。