公开(公告)号：US20130166885A1

公开(公告)日：2013-06-27

申请号：US13531013

申请日：2012-06-22

申请人： Karthik Ramani ,  Stephen Presant ,  John Brothers

发明人： Karthik Ramani ,  Stephen Presant ,  John Brothers

IPC分类号： G01K3/00 ,  G06F9/30

CPC分类号： G06F9/4893 ,  G01K7/427 ,  G06F1/20 ,  Y02D10/24

摘要： When an instruction is executed on an integrated circuit (IC), an activity level and temperature are measured. A relationship between the activity level and temperature is determined, to estimate the temperature from the activity level. The activity level is monitored and is input to a scheduler, which estimates the IC temperature based on the activity level. The scheduler distributes work taking into account the temperature of various IC regions and may include distributing work to the IC region that has a lowest estimated temperature or relatively lower estimated temperature (e.g., lower than the average IC or IC region temperature). When the utilization level of one or more IC regions is high, the scheduler is configured to reduce the clock speed or the voltage of the one or more IC regions, or flag the regions as being unavailable for additional workload.

摘要翻译： 当在集成电路（IC）上执行指令时，测量活动电平和温度。 确定活动水平和温度之间的关系，从活动水平估算温度。 监视活动级别，并将其输入到调度程序中，该调度程序将根据活动级别估算IC温度。 调度器考虑各种IC区域的温度来分配工作，并且可以包括将工作分配到具有最低估计温度或相对较低估计温度（例如低于平均IC或IC区域温度）的IC区域。 当一个或多个IC区域的使用级别高时，调度器被配置为降低一个或多个IC区域的时钟速度或电压，或将该区域标记为不可用于额外的工作负载。

公开(公告)号：US08803897B2

公开(公告)日：2014-08-12

申请号：US12616636

申请日：2009-11-11

申请人： Greg Sadowski ,  Konstantine Iourcha ,  John Brothers

发明人： Greg Sadowski ,  Konstantine Iourcha ,  John Brothers

IPC分类号： G06F13/00

CPC分类号： G06F9/3879 ,  G06F9/544

摘要： Disclosed herein is a graphics-processing unit (GPU) having an internal memory for general-purpose use and applications thereof. Such a GPU includes a first internal memory, an execution unit coupled to the first internal memory, and an interface configured to couple the first internal memory to a second internal memory of an other processing unit. The first internal memory may comprise a stacked dynamic random access memory (DRAM) or an embedded DRAM. The interface may be further configured to couple the first internal memory to a display device. The GPU may also include another interface configured to couple the first internal memory to a central processing unit. In addition, the GPU may be embodied in software and/or included in a computing system.

摘要翻译： 这里公开了具有用于通用目的的内部存储器和其应用的图形处理单元（GPU）。 这样的GPU包括第一内部存储器，耦合到第一内部存储器的执行单元和被配置为将第一内部存储器耦合到另一个处理单元的第二内部存储器的接口。 第一内部存储器可以包括堆叠的动态随机存取存储器（DRAM）或嵌入式DRAM。 接口可以被进一步配置成将第一内部存储器耦合到显示装置。 GPU还可以包括被配置为将第一内部存储器耦合到中央处理单元的另一接口。 此外，GPU可以体现在软件中和/或包括在计算系统中。

公开(公告)号：US08368701B2

公开(公告)日：2013-02-05

申请号：US12266034

申请日：2008-11-06

申请人： Timour Paltashev ,  Boris Prokopenko ,  John Brothers

发明人： Timour Paltashev ,  Boris Prokopenko ,  John Brothers

IPC分类号： G06F15/00 ,  G06F1/00 ,  G06T1/20 ,  G06T1/00 ,  G06T15/00

CPC分类号： G06T1/20 ,  G06F9/30072 ,  G06F9/30094 ,  G06F9/3867 ,  G06F9/3877 ,  G06F9/3885 ,  G06F9/3897 ,  G06F13/14 ,  G06F15/7867

摘要： Included are embodiments of systems and methods for processing metacommands. In at least one exemplary embodiment a Graphics Processing Unit (GPU) includes a metaprocessor configured to process at least one context register, the metaprocessor including context management logic and a metaprocessor control register block coupled to the metaprocessor, the metaprocessor control register block configured to receive metaprocessor configuration data, the metaprocessor control register block further configured to define metacommand execution logic block behavior. Some embodiments include a Bus Interface Unit (BIU) configured to provide the access from a system processor to the metaprocessor and a GPU command stream processor configured to fetch a current context command stream and send commands for execution to a GPU pipeline and metaprocessor.

摘要翻译： 包括用于处理元命令的系统和方法的实施例。 在至少一个示例性实施例中，图形处理单元（GPU）包括配置成处理至少一个上下文寄存器的元处理器，所述元处理器包括上下文管理逻辑和耦合到元处理器的元处理器控制寄存器块，所述元处理器控制寄存器块被配置为接收 元处理器配置数据，元处理器控制寄存器块进一步配置为定义metacommand执行逻辑块行为。 一些实施例包括被配置为提供从系统处理器到元处理器的访问的总线接口单元（BIU）以及被配置为获取当前上下文命令流并且发送用于执行到GPU流水线和元处理器的命令的GPU命令流处理器。

公开(公告)号：US07551176B2

公开(公告)日：2009-06-23

申请号：US11466861

申请日：2006-08-24

申请人： Fred Liao ,  John Brothers

发明人： Fred Liao ,  John Brothers

IPC分类号： G06F1/00 ,  G06F13/18 ,  G09G5/36 ,  G09G5/00 ,  G09G5/02

CPC分类号： G06T15/005

摘要： Systems and method for providing shared attribute evaluation circuits in a graphics processing unit are provided. One embodiment can be described as a system for evaluating attributes in a graphics processing unit having a plurality of processing stages. The system can include an evaluation block, configured to process a plurality of attributes corresponding to a plurality of pixels and a plurality of FIFO buffers, each configured between one of the plurality of processing stages and the evaluation block. An embodiment can further include a shared buffer, configured to store the plurality of attributes or pointers during the attribute processing and processing priority logic, configured to determine a plurality of priorities corresponding to the plurality of attributes.

摘要翻译： 提供了一种用于在图形处理单元中提供共享属性评估电路的系统和方法。 一个实施例可以被描述为用于评估具有多个处理阶段的图形处理单元中的属性的系统。 该系统可以包括评估块，其被配置为处理与多个像素相对应的多个属性和多个FIFO缓冲器，每个FIFO缓冲器被配置在多个处理级之一和评估块之间。 实施例还可以包括共享缓冲器，其被配置为在属性处理和处理优先级逻辑期间存储多个属性或指针，被配置为确定与多个属性对应的多个优先级。

公开(公告)号：US20080143733A1

公开(公告)日：2008-06-19

申请号：US11612573

申请日：2006-12-19

申请人： John Brothers

发明人： John Brothers

IPC分类号： G09G5/36

CPC分类号： G06T1/60

摘要： Provided are methods and systems for reducing memory bandwidth usage in a common buffer, multiple FIFO computing environment. The multiple FIFO's are arranged in coordination with serial processing units, such as in a pipeline processing environment. The multiple FIFO's contain pointers to entry addresses in a common buffer. Each subsequent FIFO receives only pointers that correspond to data that has not been rejected by the corresponding processing unit. Rejected pointers are moved to a free list for reallocation to later data.

摘要翻译： 提供了用于减少公共缓冲器，多个FIFO计算环境中的存储器带宽使用的方法和系统。 多个FIFO与串行处理单元协调配置，例如在流水线处理环境中。 多个FIFO包含指向公共缓冲区中的入口地址的指针。 每个后续FIFO仅接收与未被相应处理单元拒绝的数据相对应的指针。 被拒绝的指针被移动到空闲列表，以重新分配给稍后的数据。

公开(公告)号：US20080049031A1

公开(公告)日：2008-02-28

申请号：US11466861

申请日：2006-08-24

申请人： Fred Liao ,  John Brothers

发明人： Fred Liao ,  John Brothers

IPC分类号： G06T1/60

CPC分类号： G06T15/005

摘要： Systems and method for providing shared attribute evaluation circuits in a graphics processing unit are provided. One embodiment can be described as a system for evaluating attributes in a graphics processing unit having a plurality of processing stages. The system can include an evaluation block, configured to process a plurality of attributes corresponding to a plurality of pixels and a plurality of FIFO buffers, each configured between one of the plurality of processing stages and the evaluation block. An embodiment can further include a shared buffer, configured to store the plurality of attributes or pointers during the attribute processing and processing priority logic, configured to determine a plurality of priorities corresponding to the plurality of attributes.

摘要翻译： 提供了一种用于在图形处理单元中提供共享属性评估电路的系统和方法。 一个实施例可以被描述为用于评估具有多个处理阶段的图形处理单元中的属性的系统。 该系统可以包括评估块，其被配置为处理与多个像素相对应的多个属性和多个FIFO缓冲器，每个FIFO缓冲器被配置在多个处理级之一和评估块之间。 实施例还可以包括共享缓冲器，其被配置为在属性处理和处理优先级逻辑期间存储多个属性或指针，被配置为确定与多个属性对应的多个优先级。

公开(公告)号：US20070297501A1

公开(公告)日：2007-12-27

申请号：US11760247

申请日：2007-06-08

申请人： Zahid Hussain ,  Huy Bui ,  John Brothers

发明人： Zahid Hussain ,  Huy Bui ,  John Brothers

IPC分类号： H04B1/66

CPC分类号： H04N19/436 ,  H04N19/13 ,  H04N19/176 ,  H04N19/197 ,  H04N19/44 ,  H04N19/46 ,  H04N19/61 ,  H04N19/70

摘要： Various embodiments of decoding systems and methods are disclosed. One system embodiment, among others, comprises a software programmable core processing unit having a variable length decoding unit (VLD) unit configured to execute a shader, the shader configured to selectively implement decoding of a video stream coded based on a plurality of different coding methods to provide a decoded data output, wherein the decoding is implemented using a combination of software and hardware.

摘要翻译： 公开了解码系统和方法的各种实施例。 一个系统实施例包括具有被配置为执行着色器的可变长度解码单元（VLD）单元的软件可编程核心处理单元，该着色器被配置为选择性地实现基于多种不同编码方法编码的视频流的解码 以提供解码数据输出，其中使用软件和硬件的组合来实现解码。

公开(公告)号：US20070296613A1

公开(公告)日：2007-12-27

申请号：US11760274

申请日：2007-06-08

申请人： Zahid Hussain ,  Huy Bui ,  John Brothers

发明人： Zahid Hussain ,  Huy Bui ,  John Brothers

IPC分类号： H03M7/00

CPC分类号： H04N19/625 ,  H04N19/42 ,  H04N19/436 ,  H04N19/61 ,  H04N19/91

摘要： Various embodiments of decoding systems and methods are disclosed. One method embodiment, among others, comprises providing a shader configurable with a plurality of instruction sets to decode a video stream coded a plurality of different coding methods, loading the shader having one of the plurality of instruction sets to a variable length decoding (VLD) unit of a software programmable core processing unit for execution thereof, and decoding the video stream by executing the shader on the VLD unit.

摘要翻译： 公开了解码系统和方法的各种实施例。 一个方法实施例包括提供可配置有多个指令集的着色器，以对编码多个不同编码方法的视频流进行解码，将具有多个指令集中的一个的着色器加载到可变长度解码（VLD）中， 用于执行它的软件可编程核心处理单元的单元，以及通过在VLD单元上执行着色器来解码视频流。

公开(公告)号：US08004533B2

公开(公告)日：2011-08-23

申请号：US11530052

申请日：2006-09-08

申请人： Hsilin Huang ,  Boris Prokopenko ,  John Brothers

发明人： Hsilin Huang ,  Boris Prokopenko ,  John Brothers

IPC分类号： G06T1/20

CPC分类号： G06F9/542 ,  G06F9/3879 ,  G06F9/485 ,  G06F9/526 ,  G06T1/20

摘要： A command parser in a GPU is configured to schedule execution of received commands and includes a first input coupled to a scheduler. The first command parser input is configured to communicate bus interface commands to the command parser for execution. A second command parser input is coupled to a controller that receives ring buffer commands from the scheduler in association with a new or previously-partially executed ring buffer, or context, which are executed by the command parser. A third command parser input coupled to a command DMA component that receives DMA commands from the controller that are also contained in the new or previously-partially executed ring buffer, which are forwarded to the command parser for execution. The command parser forwards data corresponding to commands received on one or more the first, second, and third inputs via one or more outputs.

摘要翻译： GPU中的命令解析器被配置为调度所接收命令的执行，并且包括耦合到调度器的第一输入。 第一个命令解析器输入被配置为将总线接口命令传递给命令解析器以供执行。 第二命令解析器输入耦合到控制器，该控制器从由调度器接收环形缓冲器命令，与由命令解析器执行的新的或先前部分执行的环形缓冲器或上下文相关联。 第三个命令解析器输入耦合到命令DMA组件，该组件接收来自控制器的DMA命令，该命令也包含在新的或先前部分执行的环形缓冲器中，这些命令被转发到命令解析器以供执行。 命令解析器经由一个或多个输出转发对应于在一个或多个第一，第二和第三输入上接收的命令的数据。

公开(公告)号：US07755632B2

公开(公告)日：2010-07-13

申请号：US11552649

申请日：2006-10-25

申请人： John Brothers ,  Hsilin Huang ,  Boris Prokopenko

发明人： John Brothers ,  Hsilin Huang ,  Boris Prokopenko

IPC分类号： G06F13/00

CPC分类号： G06F9/542 ,  G06F9/3879 ,  G06F9/485 ,  G06F9/526 ,  G06T1/20

摘要： A GPU pipeline is synchronized by sending a fence command from a first module to an addressed synchronization register pair. Fence command associated data may be stored in a fence register of the addressed register pair. A second module sends a wait command with associated data to the addressed register pair, which may be compared to the data in the fence register. If the fence register data is greater than or equal to the wait command associated data, the second module may be acknowledged for sending the wait command and released for processing other graphics operations. If the fence register data is less than the wait command associated data, the second module is stalled until subsequent receipt of a fence command having data that is greater than or equal to the wait command associated data, which may be written to a wait register associated to the addressed register pair.

摘要翻译： 通过从第一模块发送fence命令到寻址的同步寄存器对来同步GPU流水线。 栅栏命令相关数据可以存储在寻址的寄存器对的栅栏寄存器中。 第二个模块发送一个具有关联数据的等待命令到寻址的寄存器对，这可以与围栏寄存器中的数据进行比较。 如果栅栏寄存器数据大于等于等待命令关联数据，则可以确认第二模块用于发送等待命令并被释放用于处理其他图形操作。 如果栅栏寄存器数据小于等待命令相关联的数据，则第二模块停止，直到后续接收到具有大于或等于等待命令关联数据的数据的围栏命令，该等待命令可被写入等待寄存器 到寻址寄存器对。