公开(公告)号：US20050270859A1

公开(公告)日：2005-12-08

申请号：US11198221

申请日：2005-08-08

申请人： Yoshiharu Kato

发明人： Yoshiharu Kato

IPC分类号： G01R31/28 ,  G11C29/02 ,  G11C29/36 ,  G11C5/00

CPC分类号： G11C29/025 ,  G01R31/2853 ,  G11C29/02 ,  G11C29/36

摘要： A method of testing an electronic device including first and second semiconductor devices connected to each other with a plurality of bus lines. First, the first semiconductor device supplies a selected one of the bus lines with a first logical output signal. Then, the second semiconductor device acquires a first bus line signal from the selected bus line. The second semiconductor device inverts the first bus line signal to generate a second logical output signal. The second semiconductor device transmits the second logical output signal to the first semiconductor device. The first semiconductor device receives a second bus line signal from the selected bus line. The first semiconductor device compares the first logical output signal and the second bus line signal to detect a connection between the first semiconductor device and the second semiconductor device.

摘要翻译： 一种测试电子设备的方法，该电子设备包括用多个总线线路彼此连接的第一和第二半导体器件。 首先，第一半导体器件向所选择的总线线路提供第一逻辑输出信号。 然后，第二半导体器件从所选择的总线获取第一总线信号。 第二半导体器件使第一总线信号反相以产生第二逻辑输出信号。 第二半导体器件将第二逻辑输出信号发送到第一半导体器件。 第一半导体器件从所选择的总线接收第二总线信号。 第一半导体器件比较第一逻辑输出信号和第二总线信号以检测第一半导体器件和第二半导体器件之间的连接。

公开(公告)号：US06546019B1

公开(公告)日：2003-04-08

申请号：US09150232

申请日：1998-09-10

申请人： Yoshiharu Kato ,  Ryo Takajitsuko ,  Hidetoshi Iwasa ,  Kiyofumi Mitsuze

发明人： Yoshiharu Kato ,  Ryo Takajitsuko ,  Hidetoshi Iwasa ,  Kiyofumi Mitsuze

IPC分类号： H04L12413

CPC分类号： H04L49/90 ,  H04L69/40

摘要： A duplex memory control apparatus having a first control unit containing a first memory and a second control unit containing second memory, a first control unit and a second control unit connected to each other through a bus. The first control unit having a central processing unit writing write data in the first memory; a transmitter obtaining the write data to be written in the first memory by the central processing unit, a transmitter, when a write data can be specified based on another write data previously obtained, transmitting specific data smaller than a write data to the second control unit instead of the write data; a first bus mutually connecting the central processing unit, the first memory an the transmitter; a first direct memory access unit reading the write data held int eh first memory through the first but; a second bus connected with a first direct memory access unit; and an access limiter connected to the first bus and the second bus and limiting to use the first bus by the first direct memory access unit when the central processing unit uses the first bus. The second control unit having a data producing section receiving the specific data from the transmitter and producing an original write data based on the specific data; and a second direct memory access unit writing the original write data produced by the data producing section into the second memory.

摘要翻译： 一种双工存储器控制装置，具有包含第一存储器的第一控制单元和包含第二存储器的第二控制单元，通过总线相互连接的第一控制单元和第二控制单元。 第一控制单元具有中央处理单元，将写数据写入第一存储器; 发送器，当可以基于先前获得的另一个写入数据来指定写入数据时，将小于写入数据的特定数据发送到第二控制单元，所述发送器通过中央处理单元获得要写入第一存储器的写入数据; 而不是写入数据; 相互连接中央处理单元的第一总线，第一存储器和发送器; 第一直接存储器存取单元，通过第一个读取第一个存储器中保存的写入数据; 与第一直接存储器存取单元连接的第二总线; 以及连接到第一总线和第二总线的访问限制器，并且当中央处理单元使用第一总线时，限制第一直接存储器访问单元使用第一总线。 所述第二控制单元具有从所述发送器接收所述特定数据的数据产生部分，并且基于所述特定数据产生原始写入数据; 以及第二直接存储器访问单元，将由数据产生部分产生的原始写入数据写入第二存储器。

公开(公告)号：US06529523B1

公开(公告)日：2003-03-04

申请号：US09130159

申请日：1998-08-06

申请人： Yoshiharu Kato

发明人： Yoshiharu Kato

IPC分类号： H04L1266

CPC分类号： H04L49/30 ,  H04L12/5602 ,  H04L12/6402 ,  H04L49/103 ,  H04L49/20 ,  H04L49/254 ,  H04L49/255 ,  H04L49/3009 ,  H04L49/3081 ,  H04L49/503 ,  H04L49/606 ,  H04L2012/5632 ,  H04Q11/0478

摘要： The sending/receiving unit of an STM switch is provided with a converting circuit for converting time division multiplexed frames of an STM network to cells of an ATM network and a converting circuit for converting cells of an ATM network to time division multiplexed frames of an STM network. The STM switch time division multiplexes data from terminals, converts the time division multiplexed frame to cells and sends the cells to an ATM switch. Cells switched by an ATM switch and sent to the STM switch are converted to time division multiplexed frames by the STM switch, whence the frames are sent to prescribed terminals.

摘要翻译： STM交换机的发送/接收单元设置有用于将STM网络的时分多路复用帧转换为ATM网络的小区的转换电路和用于将ATM网络的小区转换成STM的时分多路复用帧的转换电路 网络。 STM切换时分复用来自终端的数据，将时分复用帧转换为小区，并将该小区发送到ATM交换机。 由ATM交换机切换并发送到STM交换机的小区由STM交换机转换为时分多路复用帧，从而将帧发送到规定的终端。

公开(公告)号：US06512765B1

公开(公告)日：2003-01-28

申请号：US09228672

申请日：1999-01-12

申请人： Yoshiharu Kato ,  Ryo Takajitsuko ,  Hidetoshi Iwasa ,  Kiyofumi Mitsuze

发明人： Yoshiharu Kato ,  Ryo Takajitsuko ,  Hidetoshi Iwasa ,  Kiyofumi Mitsuze

IPC分类号： H04J1100

CPC分类号： H04Q11/04 ,  H04J3/08 ,  H04J2203/0012 ,  H04J2203/0039 ,  H04J2203/006 ,  H04J2203/0067 ,  H04Q2213/13003 ,  H04Q2213/13292 ,  H04Q2213/13299 ,  H04Q2213/13367 ,  H04Q2213/1338 ,  H04Q2213/13393

摘要： An exchange equipment using STM able to achieve an improvement of an efficiency of use and an improvement of ease of increase of terminal cards, that is, an STM type exchange, including a time switch, for performing exchange processing of time division multiplexed data, wherein a ring highway is connected via a terminal common unit to an upstream highway and a downstream highway coupled to this time switch via a highway interface unit or directly and wherein a plurality of terminal cards are connected to this ring highway. Each terminal card is provided with an add/drop unit which drops and adds the data from and to an assigned time slot on the ring highway according to control information indicating time slot assignment information determined by the control unit and adds the data and with a card control unit which controls the add/drop unit.

摘要翻译： 使用STM的交换设备能够实现提高使用效率和提高终端卡的容易性，即包括时间转换的STM类型交换机，用于执行时分多路复用数据的交换处理，其中 环形高速公路通过终端公共单元经由高速公路接口单元或直接连接到上游公路和与该时间交换机相连的下游公路，并且其中多个终端卡连接到该环形高速公路。 每个终端卡具有一个添加/分出单元，根据控制信息指示由控制单元确定的时隙分配信息，并将数据和卡片相加，从而从环形高速公路上的分配时隙中删除数据并将其添加到分配的时隙 控制单元控制加/减单元。

公开(公告)号：US06492850B2

公开(公告)日：2002-12-10

申请号：US10159129

申请日：2002-06-03

申请人： Yoshiharu Kato ,  Nobuyoshi Wakasugi

发明人： Yoshiharu Kato ,  Nobuyoshi Wakasugi

IPC分类号： H03K1722

CPC分类号： G05F1/465

摘要： The invention aims at securely generating an internal supply voltage when turning on the power supply of internal circuits in a semiconductor integrated circuit where the operation voltage is low, and securely resetting the internal circuits. The voltage generator generates an internal supply voltage supplied to the internal circuits based on the reference voltage by using the external supply voltage supplied from the exterior. That is, the voltage generator forcibly supplies the external supply voltage as internal supply voltage when the power-on reset signal is activated. Therefore, when the external supply voltage is low at the time of turning-on of the power, and the voltage generator does not operate normally, the internal supply voltage can be securely generated following the external supply voltage so as to be supplied to the internal circuits.

摘要翻译： 本发明的目的是在接通工作电压低的半导体集成电路中的内部电路的电源供应时可靠地产生内部电源电压，并可靠地复位内部电路。 电压发生器通过使用从外部提供的外部电源电压，基于参考电压产生提供给内部电路的内部电源电压。 也就是说，当上电复位信号被激活时，电压发生器强制提供外部电源电压作为内部电源电压。 因此，当电源接通时外部电源电压低时，电压发生器不能正常工作时，可以根据外部电源电压可靠地产生内部电源电压，从而供给到内部 电路。

公开(公告)号：US06472929B2

公开(公告)日：2002-10-29

申请号：US09927371

申请日：2001-08-13

申请人： Isamu Kobayashi ,  Yoshiharu Kato ,  Takahiro Yokoyama

发明人： Isamu Kobayashi ,  Yoshiharu Kato ,  Takahiro Yokoyama

IPC分类号： G05F110

CPC分类号： G05F3/242

摘要： A semiconductor device which is capable of shutting off the influence of noise introduced into a reference voltage while preventing an increase in die size. The semiconductor device including a reference potential generator, first and second filter, and first and second input circuit. The reference potential generator generates a reference potential in accordance with a first power supply. The first filter is connected to the first power supply and filters the reference potential to generate a first filtered reference potential. The second filter is connected to a second power supply and filters the reference potential to generate a second filtered reference potential. The first input circuit is connected to the first power supply and receives the first filtered reference potential to generate a first predetermined voltage. The second input circuit is connected to the second power supply and receives the second filtered reference potential to generate a second predetermined voltage.

摘要翻译： 一种半导体器件，其能够在阻止芯片尺寸增大的同时，切断引入参考电压的噪声的影响。 该半导体器件包括参考电位发生器，第一和第二滤波器以及第一和第二输入电路。 参考电位发生器根据第一电源产生参考电位。 第一滤波器连接到第一电源并对参考电位进行滤波以产生第一滤波参考电位。 第二滤波器连接到第二电源并对参考电势进行滤波以产生第二滤波参考电位。 第一输入电路连接到第一电源并且接收第一滤波参考电位以产生第一预定电压。 第二输入电路连接到第二电源并接收第二滤波参考电位以产生第二预定电压。

公开(公告)号：US5555210A

公开(公告)日：1996-09-10

申请号：US305880

申请日：1994-09-15

申请人： Yoshiharu Kato

发明人： Yoshiharu Kato

IPC分类号： G11C11/409 ,  G11C7/06 ,  G11C7/10 ,  G11C7/00

CPC分类号： G11C7/065 ,  G11C7/1078

摘要： A semiconductor memory device writes data to memory cells contained in the memory device in response to an enable signal supplied thereto. The memory device includes, a pair of bit lines connected to the memory cells, and a sense amplifier connected to the pair of bit lines to latch cell data read from the memory cells. The pair of bit lines couples to a data writing circuit, which writes data to the memory cells in response to the first enable signal. The memory device also includes a switching circuit connected to the sense amplifier, for disabling the sense amplifier in response to the first enable signal.

摘要翻译： 半导体存储器件响应于提供给其的使能信号，将包含在存储器件中的存储单元写入数据。 存储器件包括连接到存储器单元的一对位线，以及连接到一对位线的读出放大器，以锁存从存储器单元读取的单元数据。 一对位线耦合到数据写入电路，其响应于第一使能信号将数据写入存储器单元。 存储器件还包括连接到读出放大器的开关电路，用于响应于第一使能信号禁止读出放大器。

公开(公告)号：US5553066A

公开(公告)日：1996-09-03

申请号：US307109

申请日：1994-09-16

申请人： Yoshiharu Kato ,  Ryouzi Takano ,  Takashi Nara ,  Takashi Hatano ,  Yoshio Morita

发明人： Yoshiharu Kato ,  Ryouzi Takano ,  Takashi Nara ,  Takashi Hatano ,  Yoshio Morita

IPC分类号： H04J3/16 ,  H04J3/22 ,  H04M3/00 ,  H04Q11/04

CPC分类号： H04J3/1694 ,  H04J3/1647 ,  H04J3/22 ,  H04J3/0626

摘要： A data transfer system including an exchange, wherein the exchange transfers data by sharing a plurality of channels by a time division multiplex mode. In this case, the exchange transfers the data by variably allocating respective time slots to be occupied by the respective channels. That is, it is possible to allot any line speed to any channel and therefore possible to mix signals with different data transfer speeds in the frames. This results in an exchange network with a high degree of freedom of transfer for the subscriber terminal equipment.

摘要翻译： 一种包括交换机的数据传输系统，其中所述交换机通过以时分复用模式共享多个信道来传送数据。 在这种情况下，交换机通过可变地分配要由相应信道占用的各个时隙来传送数据。 也就是说，可以将任何线路速度分配给任何通道，因此可以将不同数据传输速度的信号混合在帧中。 这导致用户终端设备具有高传输自由度的交换网络。

公开(公告)号：US5523999A

公开(公告)日：1996-06-04

申请号：US407801

申请日：1995-03-20

申请人： Ryouzi Takano ,  Masataka Sakai ,  Sumie Morita ,  Kiyohumi Mitsuze ,  Yoshiharu Kato

发明人： Ryouzi Takano ,  Masataka Sakai ,  Sumie Morita ,  Kiyohumi Mitsuze ,  Yoshiharu Kato

IPC分类号： H04L12/951 ,  H04J3/02

CPC分类号： H04L12/56

摘要： A packet data switching system having packet switching equipment and a plurality of transfer control units cooperating with the packet switching equipment exchanging packet data to be transferred through the transfer control units. In the system each packet data is divided into packet frames each having the same frame length and all the packet frames are processed synchronously in each of the transfer control units. Each of the packet frames is composed of a header area and data area. The header area is used for indicating transfer control information, such as an address of a destination transfer control unit and a continuous transmission flag which denotes that the related packet frame should be exchanged to the same destination as that of the preceding packet frame.

摘要翻译： 具有分组交换设备的分组数据交换系统和与分组交换设备协作的多个传送控制单元，交换分组数据通过传送控制单元进行传送。 在该系统中，每个分组数据被分成具有相同帧长度的分组帧，并且所有分组帧在每个传送控制单元中被同步处理。 每个分组帧由报头区域和数据区域组成。 报头区域用于指示传送控制信息，例如目的地传送控制单元的地址和表示相关分组帧应当被交换到与前一分组帧相同的目的地的连续传输标志。

公开(公告)号：US5506849A

公开(公告)日：1996-04-09

申请号：US214224

申请日：1994-03-17

申请人： Yoshiharu Kato

发明人： Yoshiharu Kato

IPC分类号： G11C29/00 ,  G11C29/12 ,  G11C29/34 ,  G11C29/40 ,  G11C29/50 ,  G11C29/56 ,  G06F11/16

CPC分类号： G11C29/50012 ,  G11C29/40 ,  G11C29/50 ,  G11C11/401

摘要： Disclosed is a semiconductor memory device. A read control signal is externally input in read mode, and a test mode signal is externally input in a mode for testing memory cells. Based on the input read control signal, plural pieces of read data read out from a plurality of memory cells are latched by a plurality of latch circuits. Output signals of the latch circuits are input to a data compressor, which checks if the output signals of the latch circuits are the same and outputs a resultant signal in a form of compressed data of one bit. The output signal of the data compressor is input to an output circuit, which outputs the output signal of the data compressor based on the input test mode signal. A preset circuit allows the latch circuits to latch different pieces of data based on the test mode signal and the read control signal.

摘要翻译： 公开了一种半导体存储器件。 在读取模式下外部输入读取控制信号，并且在用于测试存储器单元的模式中外部输入测试模式信号。 基于输入读取控制信号，从多个存储单元读出的多条读取数据被多个锁存电路锁存。 锁存电路的输出信号被输入到数据压缩器，该压缩器检查锁存电路的输出信号是否相同，并以一位压缩数据的形式输出合成信号。 数据压缩器的输出信号被输入到输出电路，输出电路基于输入的测试模式信号输出数据压缩器的输出信号。 预置电路允许锁存电路基于测试模式信号和读取控制信号来锁存不同数据。