公开(公告)号：US07386844B2

公开(公告)日：2008-06-10

申请号：US10760429

申请日：2004-01-21

申请人： Taketo Heishi ,  Hajime Ogawa ,  Takenobu Tani ,  Yukihiro Sasagawa

发明人： Taketo Heishi ,  Hajime Ogawa ,  Takenobu Tani ,  Yukihiro Sasagawa

IPC分类号： G06F9/45 ,  G06F1/00 ,  G06F1/26

CPC分类号： G06F9/3001 ,  G06F8/4432 ,  G06F9/30156 ,  G06F9/3836 ,  G06F9/3838 ,  Y02D10/41

摘要： A compiler apparatus is capable of generating instruction sequences causing a processor to operate with lower power consumption. The compiler apparatus translates a source program into a machine language program for a processor including execution units which can execute instructions in parallel, and including instruction issue units which issue the instructions executed, respectively, by the execution units. The compiler apparatus includes a parser unit operable to parse the source program, an intermediate code conversion unit operable to convert the parsed source program into intermediate codes, an optimization unit operable to optimize the intermediate codes to reduce a hamming distance between instructions from the same instruction issue unit in consecutive instruction cycles, and includes a code generation unit operable to convert the optimized intermediate codes into machine language instructions.

摘要翻译： 编译装置能够产生指令序列，使得处理器以更低的功耗进行操作。 编译装置将源程序转换为用于处理器的机器语言程序，所述处理器包括可并行执行指令的执行单元，并且包括执行单元分别执行执行指令的指令发布单元。 编译器装置包括可解析源程序的解析器单元，可操作以将解析的源程序转换为中间代码的中间代码转换单元，可优化中间代码以减少来自相同指令的指令之间的汉明距离的优化单元 发布单元，并且包括可以将优化的中间代码转换成机器语言指令的代码生成单元。

公开(公告)号：US20080046690A1

公开(公告)日：2008-02-21

申请号：US11896370

申请日：2007-08-31

申请人： Tetsuya Tanaka ,  Hazuki Okabayashi ,  Taketo Heishi ,  Hajime Ogawa ,  Tsuneyuki Suzuki ,  Tokuzo Kiyohara ,  Takeshi Tanaka ,  Hideshi Nishida ,  Masaki Maeda

发明人： Tetsuya Tanaka ,  Hazuki Okabayashi ,  Taketo Heishi ,  Hajime Ogawa ,  Tsuneyuki Suzuki ,  Tokuzo Kiyohara ,  Takeshi Tanaka ,  Hideshi Nishida ,  Masaki Maeda

IPC分类号： G06F9/302

CPC分类号： G06F9/30025 ,  G06F9/30014 ,  G06F9/30021 ,  G06F9/30036 ,  G06F9/30094 ,  G06F9/30145 ,  G06F9/3016 ,  G06F9/30167

摘要： A processor according to the present invention includes a decoding unit 20, an operation unit 40 and others. When the decoding unit 20 decodes Instruction vcchk, the operation unit 40 and the like judges whether vector condition flags VC0˜VC3 (110) of a condition flag register (CFR) 32 are all zero or not, and (i) sets condition flags C4 and C5 of the condition flag register (CFR) 32 to 1 and 0, respectively, when all of the vector condition flags VC0˜VC3 are zero, and (ii) sets the condition flags C4 and C5 to 0 and 1, respectively, when not all the vector condition flags are zero. Then, the vector condition flags VC0˜VC3 are stored in the condition flags C0˜C3.

公开(公告)号：US20070256065A1

公开(公告)日：2007-11-01

申请号：US11790215

申请日：2007-04-24

申请人： Taketo Heishi ,  Toshiyuki Sakata ,  Hajime Ogawa ,  Ryoko Miyachi ,  Shuji Miyasaka ,  Tomokazu Ishikawa

发明人： Taketo Heishi ,  Toshiyuki Sakata ,  Hajime Ogawa ,  Ryoko Miyachi ,  Shuji Miyasaka ,  Tomokazu Ishikawa

IPC分类号： G06F9/45

CPC分类号： G06F8/443 ,  G06F8/425 ,  G06F8/427 ,  G06F8/4441

摘要： An operator definition file 102 and the like included in a source program 101 and a compiler 100 that translates the source program 101 into a machine language program 105 are provided. The operator definition file 102 includes definitions of various fixed point type operators by class definitions. The compiler 100 can generate effectively advanced and specific instructions that a processor executes and make improvements through expanding functions and the like without repeating frequently upgrading of the version of the compiler itself. The compiler 100 is made up of an intermediate code generation unit 121 that generates intermediate codes, a machine language instruction substitution unit 122 that substitutes the intermediate codes referring to classes defined by the operator definition file 102 with machine language instructions and an optimization unit 130 that performs optimization targeting the intermediate codes including the substituted machine language instructions.

公开(公告)号：US07237229B2

公开(公告)日：2007-06-26

申请号：US10287231

申请日：2002-11-04

申请人： Hajime Ogawa ,  Kiyohiko Sumida ,  Shuichi Takayama ,  Katsuhiro Okuno ,  Taketo Heishi

发明人： Hajime Ogawa ,  Kiyohiko Sumida ,  Shuichi Takayama ,  Katsuhiro Okuno ,  Taketo Heishi

IPC分类号： G06F9/44

CPC分类号： G06F11/3664 ,  G06F11/3624

摘要： This invention makes debugging more efficient when an object program is intended for processing a loop made up of n groups of iteration-forming instructions. Instructions in the secondary assembler program each has a combination of a line number “;lx” and an iteration identifier “;ix” attached thereto. The line number “;lx” specifies a source code from which the instruction is generated, and the iteration identifier “;ix” specifies an iteration to which the instruction belongs. When the user sets a breakpoint at an instruction, displayed in the windows are (a) a source code for generating the instruction at the breakpoint and (b) another source code for generating another instruction that belongs to a different group of iteration-forming instructions than the breakpoint instruction.

摘要翻译： 当目标程序用于处理由n组迭代形成指令组成的循环时，本发明使调试更有效。 辅助汇编程序中的指令各自具有行号“; lx”和附加到其上的迭代标识符“ix”的组合。 行号“; lx”指定生成指令的源代码，迭代标识符“ix”指定该指令所属的迭代。 当用户在指令处设置断点时，窗口中显示的是（a）用于在断点处生成指令的源代码，（b）用于产生属于不同组迭代形成指令的另一指令的另一源代码 比断点指令。

公开(公告)号：US07185176B2

公开(公告)日：2007-02-27

申请号：US10449788

申请日：2003-06-02

申请人： Tetsuya Tanaka ,  Hazuki Okabayashi ,  Taketo Heishi ,  Hajime Ogawa ,  Yoshihiro Koga ,  Manabu Kuroda ,  Masato Suzuki ,  Tokuzo Kiyohara ,  Takeshi Tanaka ,  Hideshi Nishida ,  Shuji Miyasaka

发明人： Tetsuya Tanaka ,  Hazuki Okabayashi ,  Taketo Heishi ,  Hajime Ogawa ,  Yoshihiro Koga ,  Manabu Kuroda ,  Masato Suzuki ,  Tokuzo Kiyohara ,  Takeshi Tanaka ,  Hideshi Nishida ,  Shuji Miyasaka

IPC分类号： G06F15/80

CPC分类号： G06F9/30014 ,  G06F9/30018 ,  G06F9/30036 ,  G06F9/30145 ,  G06F9/30167 ,  G06F9/3885 ,  G06F9/3887 ,  G06F15/8015

摘要： A processor according to the present invention includes a decoding unit, an operation unit and others. When the decoding unit decodes an instruction “vxaddh Rc, Ra, Rb”, an arithmetic and logic/comparison operation unit and others (i) adds the higher 16 bits of a register Ra to the lower 16 bits of the register Rb, stores the result in the higher 16 bits of a register Rc, and in parallel with this, (ii) adds the lower 16 bits of the register Ra to the higher 16 bits of the register Rb, and stores the result in the lower 16 bits of the register Rc.

摘要翻译： 根据本发明的处理器包括解码单元，操作单元等。 当解码单元解码指令“vxaddh Rc，Ra，Rb”时，算术和逻辑/比较运算单元等（i）将寄存器Ra的高16位加到寄存器Rb的低16位， 导致寄存器Rc的高16位，与此并行地，（ii）将寄存器Ra的低16位加到寄存器Rb的较高16位，并将结果存储在寄存器Rc的低16位中 注册Rc。

公开(公告)号：US07080367B2

公开(公告)日：2006-07-18

申请号：US10051335

申请日：2001-10-19

申请人： Shuichi Takayama ,  Hajime Ogawa ,  Kenichi Kawaguchi ,  Nobuo Higaki ,  Kensuke Odani ,  Tetsuya Tanaka ,  Shinya Miyaji ,  Taketo Heishi

发明人： Shuichi Takayama ,  Hajime Ogawa ,  Kenichi Kawaguchi ,  Nobuo Higaki ,  Kensuke Odani ,  Tetsuya Tanaka ,  Shinya Miyaji ,  Taketo Heishi

IPC分类号： G06F9/45

CPC分类号： G06F9/3802 ,  G06F9/30149 ,  G06F9/30152 ,  G06F9/30167 ,  G06F9/321 ,  G06F9/322 ,  G06F9/324 ,  G06F9/3822 ,  G06F9/3853

摘要： When a branch instruction is decoded by the instruction decoders 409a˜409c, the upper 29 bits of the PC relative value included in the branch instruction are sent to the upper PC calculator 411 and the lower 3 bits are sent to the lower PC calculator 405. The lower PC calculator 405 adds the lower 3 bits of the PC relative value and the lower 3 bits of the present lower PC 404 and sends the result to the lower PC 404 as the updated lower PC. The upper PC calculator 411 adds the upper 29 bits of the PC relative value, the upper 29 bits of the present upper PC 403, and a carry that may be received from the lower PC calculator 405, and sends the result to the upper PC 403 as the updated upper PC.

摘要翻译： 当分支指令由指令解码器409a〜409c解码时，分支指令中包含的PC相对值的高29位被发送到上PC计算器411，低3位被发送到下PC计算器 405。 下PC计算器405将PC相对值的低3位和当前下PC404的低3位相加，并将结果作为更新的下级PC发送到下PC404。 上PC计算器411将PC相对值的上29位，当前上位机403的上位29加上可从下PC计算器405接收的进位，并将结果发送到上PC403 作为更新的上位机。

公开(公告)号：US20060080643A1

公开(公告)日：2006-04-13

申请号：US11233023

申请日：2005-09-23

申请人： Hajime Ogawa ,  Toshiyuki Sakata

发明人： Hajime Ogawa ,  Toshiyuki Sakata

IPC分类号： G06F9/44

CPC分类号： G06F8/423 ,  G06F8/443

摘要： A program processing apparatus, which can correct a source program by automatically inserting hint information so that a satisfactory optimization can be performed even in the case where the user has not given hint information to a compiler, automatically inserts, into the source program, hint information given to the compiler, and includes: a syntax analysis unit which analyzes a syntax of the source program and generates analysis information; and a hint information insertion unit which creates a program by inserting hint information that is logically consistent and that is given to the compiler into the source program based on the analysis information, and outputs the created program.

摘要翻译： 一种程序处理装置，其可以通过自动插入提示信息来校正源程序，使得即使在用户没有向编译器提供提示信息的情况下也可以执行令人满意的优化，自动地将其提供给源程序提示信息 提供给编译器，并且包括：语法分析单元，其分析源程序的语法并生成分析信息; 以及提示信息插入单元，其通过在逻辑上一致地插入提示信息并且基于分析信息将编译器提供给源程序来创建程序，并输出所创建的程序。

公开(公告)号：US07028291B2

公开(公告)日：2006-04-11

申请号：US10191426

申请日：2002-07-10

申请人： Kiyohiko Sumida ,  Hajime Ogawa ,  Katsuhiro Okuno

发明人： Kiyohiko Sumida ,  Hajime Ogawa ,  Katsuhiro Okuno

IPC分类号： G06F9/44

CPC分类号： G06F11/3624 ,  G06F11/3628

摘要： According to the present invention, a compiler generates, as debugging information on variables appearing in a source program and the allocation of hardware resources, location information made up of elements showing, for each entry of a variable, an address range within which the variable is valid, a condition flag which is made true within the address range when the variable is valid, and a resource allocated to the variable. A debugging device analyzes the debugging information and stores it. When examining the value of a variable, an entry for the valid variable is determined from the address currently being executed and the value held in the condition flag register, and the resource allocated to that variable is obtained. In this way, the contents of the variable can be referenced correctly.

摘要翻译： 根据本发明，编译器生成作为源程序中出现的变量的调试信息和硬件资源的分配，由对于变量的每个条目表示变量的地址范围的元素组成的位置信息， 有效，当变量有效时在地址范围内成为条件标志，以及分配给该变量的资源。 调试设备分析调试信息并进行存储。 当检查变量的值时，从当前正在执行的地址和条件标志寄存器中保存的值确定有效变量的条目，并获得分配给该变量的资源。 以这种方式，可以正确地引用变量的内容。

公开(公告)号：US06976250B2

公开(公告)日：2005-12-13

申请号：US10045802

申请日：2001-10-19

申请人： Shuichi Takayama ,  Hajime Ogawa ,  Kenichi Kawaguchi ,  Nobuo Higaki ,  Kensuke Odani ,  Tetsuya Tanaka ,  Shinya Miyaji ,  Taketo Heishi

发明人： Shuichi Takayama ,  Hajime Ogawa ,  Kenichi Kawaguchi ,  Nobuo Higaki ,  Kensuke Odani ,  Tetsuya Tanaka ,  Shinya Miyaji ,  Taketo Heishi

IPC分类号： G06F9/30 ,  G06F9/32 ,  G06F9/38 ,  G06F717/151

CPC分类号： G06F9/3802 ,  G06F9/30149 ,  G06F9/30152 ,  G06F9/30167 ,  G06F9/321 ,  G06F9/322 ,  G06F9/324 ,  G06F9/3822 ,  G06F9/3853

摘要： When a branch instruction is decoded by the instruction decoders 409a˜409c, the upper 29 bits of the PC relative value included in the branch instruction are sent to the upper PC calculator 411 and the lower 3 bits are sent to the lower PC calculator 405. The lower PC calculator 405 adds the lower 3 bits of the PC relative value and the lower 3 bits of the present lower PC 404 and sends the result to the lower PC 404 as the updated lower PC. The upper PC calculator 411 adds the upper 29 bits of the PC relative value, the upper 29 bits of the present upper PC 403, and a carry that may be received from the lower PC calculator 405, and sends the result to the upper PC 403 as the updated upper PC.

摘要翻译： 当分支指令由指令解码器409a〜409c解码时，分支指令中包含的PC相对值的高29位被发送到上PC计算器411，低3位被发送到下PC计算器 405。 下PC计算器405将PC相对值的低3位和当前下PC404的低3位相加，并将结果作为更新的下级PC发送到下PC404。 上PC计算器411将PC相对值的上29位，当前上位机403的上位29加上可从下PC计算器405接收的进位，并将结果发送到上PC403 作为更新的上位机。

公开(公告)号：US06310313B1

公开(公告)日：2001-10-30

申请号：US09592576

申请日：2000-06-12

申请人： Mitsuaki Akune ,  Hajime Ogawa ,  Takashi Kanaya

发明人： Mitsuaki Akune ,  Hajime Ogawa ,  Takashi Kanaya

IPC分类号： B23H100

CPC分类号： B23H7/18

摘要： Separately from an electrode jumping operation (an amount of rise of a first electrode jump (22)) aimed at discharging machining debris produced during electrical discharge machining, an electrode jumping operation (an amount of rise of a second electrode jump (23)) is inserted for which is set an amount of rise of jump with which balls or rollers used on a sliding portion of a mechanically driving part undergo one revolution or more. Further, in a case where an abnormality of a lubricant supplying unit (101) is detected, as for a program being continued, machining is stopped after the termination of the program, or machining is stopped after continuing the program within a fixed time duration, or a program other than for machining operation is made executable.

摘要翻译： 另外，电极跳跃动作（第二电极跳跃（23））的上升的步骤与第一电极跳跃动作（第一电极跳跃（22）的上升量）相对应， 插入其中设置了在机械驱动部件的滑动部分上使用的滚珠或滚子经历一圈以上的跳跃上升量。 此外，在检测到润滑剂供给单元（101）的异常的情况下，对于继续的程序，在程序结束后停止加工，或者在固定持续时间内继续程序后停止加工， 或者可以执行除加工操作之外的程序。