公开(公告)号：US20110173289A1

公开(公告)日：2011-07-14

申请号：US12731796

申请日：2010-03-25

申请人： Dong Chen ,  Philip Heidelberger

发明人： Dong Chen ,  Philip Heidelberger

IPC分类号： G06F15/173 ,  G06F15/167

CPC分类号： G06F15/167 ,  G06F11/141

摘要： A system, method and computer program product for supporting system initiated checkpoints in parallel computing systems. The system and method generates selective control signals to perform checkpointing of system related data in presence of messaging activity associated with a user application running at the node. The checkpointing is initiated by the system such that checkpoint data of a plurality of network nodes may be obtained even in the presence of user applications running on highly parallel computers that include ongoing user messaging activity.

摘要翻译： 一种用于在并行计算系统中支持系统启动的检查点的系统，方法和计算机程序产品。 系统和方法产生选择性控制信号，以在存在与在节点处运行的用户应用程序相关联的消息传递活动的情况下执行系统相关数据的检查点。 检查点由系统启动，使得即使在存在包括正在进行的用户消息活动的高度并行计算机上的用户应用的情况下，也可以获得多个网络节点的检查点数据。

公开(公告)号：US20110104728A1

公开(公告)日：2011-05-05

申请号：US12939880

申请日：2010-11-04

申请人： Jon Y. Takemoto ,  Dong Chen

发明人： Jon Y. Takemoto ,  Dong Chen

IPC分类号： C12Q1/26 ,  C12P17/16 ,  C12N1/21 ,  C12N15/70

CPC分类号： C12P17/165 ,  C12N9/0083 ,  C12N15/70 ,  C12Y114/99003

摘要： Methods for producing biliverdin in a microorganism, methods for producing biliverdin from a non-animal source, cells for producing biliverdin and methods for producing cells for producing biliverdin are disclosed.

摘要翻译： 公开了一种微生物中生成胆色素的方法，从非动物来源产生胆色素的方法，用于产生胆色素的细胞和用于产生胆色素的细胞的制备方法。

公开(公告)号：US20090185193A1

公开(公告)日：2009-07-23

申请号：US12009424

申请日：2008-01-18

申请人： Florin Munteanu ,  Dong Chen ,  Erik L. Novak ,  G. Lawrence Best

发明人： Florin Munteanu ,  Dong Chen ,  Erik L. Novak ,  G. Lawrence Best

IPC分类号： G01B11/02

CPC分类号： G01B11/0675 ,  G01B11/0625

摘要： An explicit relationship is developed between the ratio of average interferometric modulation produced by diamond-like carbon (DLC)-coated magnetic-head surfaces and the thickness of the DLC layer. Accordingly, the thickness of the DLC layer is calculated in various manners from modulation data acquired for the system using object surfaces of known optical parameters.

摘要翻译： 在由类金刚石碳（DLC）涂覆的磁头表面产生的平均干涉调制比与DLC层的厚度之间形成明确的关系。 因此，从使用已知光学参数的物体表面的系统获取的调制数据，以各种方式计算DLC层的厚度。

公开(公告)号：US20090006808A1

公开(公告)日：2009-01-01

申请号：US11768905

申请日：2007-06-26

申请人： Matthias A. Blumrich ,  Dong Chen ,  George Chiu ,  Thomas M. Cipolla ,  Paul W. Coteus ,  Alan G. Gara ,  Mark E. Giampapa ,  Shawn Hall ,  Rudolf A. Haring ,  Philip Heidelberger ,  Gerard V. Kopcsay ,  Martin Ohmacht ,  Valentina Salapura ,  Krishnan Sugavanam ,  Todd Takken

发明人： Matthias A. Blumrich ,  Dong Chen ,  George Chiu ,  Thomas M. Cipolla ,  Paul W. Coteus ,  Alan G. Gara ,  Mark E. Giampapa ,  Shawn Hall ,  Rudolf A. Haring ,  Philip Heidelberger ,  Gerard V. Kopcsay ,  Martin Ohmacht ,  Valentina Salapura ,  Krishnan Sugavanam ,  Todd Takken

IPC分类号： G06F15/80 ,  G06F9/06

CPC分类号： G06F15/17337

摘要： A novel massively parallel supercomputer of petaOPS-scale includes node architectures based upon System-On-a-Chip technology, where each processing node comprises a single Application Specific Integrated Circuit (ASIC) having up to four processing elements. The ASIC nodes are interconnected by multiple independent networks that optimally maximize the throughput of packet communications between nodes with minimal latency. The multiple networks may include three high-speed networks for parallel algorithm message passing including a Torus, collective network, and a Global Asynchronous network that provides global barrier and notification functions. These multiple independent networks may be collaboratively or independently utilized according to the needs or phases of an algorithm for optimizing algorithm processing performance. Novel use of a DMA engine is provided to facilitate message passing among the nodes without the expenditure of processing resources at the node.

摘要翻译： petaOPS规模的一种新型大规模并行超级计算机包括基于片上系统技术的节点架构，其中每个处理节点包括具有多达四个处理元件的单个专用集成电路（ASIC）。 ASIC节点通过多个独立网络互连，以最小的延迟最大化节点之间的数据包通信的吞吐量。 多个网络可以包括用于并行算法消息传递的三个高速网络，包括Torus，集合网络和提供全局障碍和通知功能的全球异步网络。 这些多个独立网络可以根据用于优化算法处理性能的算法的需求或阶段来协同或独立地利用。 提供了新的使用DMA引擎来促进节点之间的消息传递，而不需要节点处理资源。

公开(公告)号：US20090006672A1

公开(公告)日：2009-01-01

申请号：US11768800

申请日：2007-06-26

申请人： Matthias A. Blumrich ,  Dong Chen ,  Alan G. Gara ,  Mark E. Giampapa ,  Philip Heidelberger ,  Martin Ohmacht ,  Valentina Salapura ,  Pavlos Vranas

发明人： Matthias A. Blumrich ,  Dong Chen ,  Alan G. Gara ,  Mark E. Giampapa ,  Philip Heidelberger ,  Martin Ohmacht ,  Valentina Salapura ,  Pavlos Vranas

IPC分类号： G06F3/00 ,  G06F1/04

CPC分类号： G06F12/0835 ,  G06F12/0831

摘要： An apparatus and method for tracking coherence event signals transmitted in a multiprocessor system. The apparatus comprises a coherence logic unit, each unit having a plurality of queue structures with each queue structure associated with a respective sender of event signals transmitted in the system. A timing circuit associated with a queue structure controls enqueuing and dequeuing of received coherence event signals, and, a counter tracks a number of coherence event signals remaining enqueued in the queue structure and dequeued since receipt of a timestamp signal. A counter mechanism generates an output signal indicating that all of the coherence event signals present in the queue structure at the time of receipt of the timestamp signal have been dequeued. In one embodiment, the timestamp signal is asserted at the start of a memory synchronization operation and, the output signal indicates that all coherence events present when the timestamp signal was asserted have completed. This signal can then be used as part of the completion condition for the memory synchronization operation.

摘要翻译： 一种用于跟踪在多处理器系统中发送的相干事件信号的装置和方法。 该装置包括相干逻辑单元，每个单元具有多个队列结构，每个队列结构与在系统中传输的事件信号的相应发送者相关联。 与队列结构相关联的定时电路控制接收的相干事件信号的排队和出队，并且计数器跟踪队列结构中剩余入队的多个相干事件信号，并且从接收到时间戳信号起出队。 计数器机构产生一个输出信号，指示在接收时间戳信号时存在于队列结构中的所有相干事件信号已经出队。 在一个实施例中，时间戳信号在存储器同步操作的开始被断言，并且输出信号指示当时间戳信号被断言时存在的所有相干事件已经完成。 然后可以将该信号用作存储器同步操作的完成条件的一部分。

公开(公告)号：US20090006666A1

公开(公告)日：2009-01-01

申请号：US11768781

申请日：2007-06-26

申请人： Dong Chen ,  Alan G. Gara ,  Philip Heidelberger ,  Pavlos Vranas

发明人： Dong Chen ,  Alan G. Gara ,  Philip Heidelberger ,  Pavlos Vranas

IPC分类号： G06F13/28

CPC分类号： G06F13/28 ,  Y02D10/14

摘要： A parallel computer system is constructed as a network of interconnected compute nodes. Each of the compute nodes includes at least one processor, a memory and a DMA engine. The DMA engine includes a processor interface for interfacing with the at least one processor, DMA logic, a memory interface for interfacing with the memory, a DMA network interface for interfacing with the network, injection and reception byte counters, injection and reception FIFO metadata, and status registers and control registers. The injection FIFOs maintain memory locations of the injection FIFO metadata memory locations including its current head and tail, and the reception FIFOs maintain the reception FIFO metadata memory locations including its current head and tail. The injection byte counters and reception byte counters may be shared between messages.

摘要翻译： 并行计算机系统被构造为互连计算节点的网络。 每个计算节点包括至少一个处理器，存储器和DMA引擎。 DMA引擎包括用于与至少一个处理器连接的处理器接口，DMA逻辑，用于与存储器连接的存储器接口，用于与网络接口的DMA网络接口，注入和接收字节计数器，注入和接收FIFO元数据， 和状态寄存器和控制寄存器。 注入FIFO保持注入FIFO元数据存储器位置的存储器位置，包括其当前头部和尾部，并且接收FIFO保持包括其当前头部和尾部的接收FIFO元数据存储器位置。 注入字节计数器和接收字节计数器可以在消息之间共享。

公开(公告)号：US20090006296A1

公开(公告)日：2009-01-01

申请号：US11768795

申请日：2007-06-26

申请人： Dong Chen ,  Alan G. Gara ,  Mark E. Giampapa ,  Philip Heidelberger ,  Burkhard Steinmacher-Burow ,  Pavlos Vranas

发明人： Dong Chen ,  Alan G. Gara ,  Mark E. Giampapa ,  Philip Heidelberger ,  Burkhard Steinmacher-Burow ,  Pavlos Vranas

IPC分类号： G06F15/18

CPC分类号： G06F15/163

摘要： A parallel computer system is constructed as a network of interconnected compute nodes to operate a global message-passing application for performing communications across the network. Each of the compute nodes includes one or more individual processors with memories which run local instances of the global message-passing application operating at each compute node to carry out local processing operations independent of processing operations carried out at other compute nodes. Each compute node also includes a DMA engine constructed to interact with the application via Injection FIFO Metadata describing multiple Injection FIFOs where each Injection FIFO may containing an arbitrary number of message descriptors in order to process messages with a fixed processing overhead irrespective of the number of message descriptors included in the Injection FIFO.

摘要翻译： 并行计算机系统被构造为互连的计算节点的网络，以操作用于在整个网络上执行通信的全局消息传递应用。 每个计算节点包括具有存储器的一个或多个单独处理器，该存储器运行在每个计算节点处操作的全局消息传递应用的本地实例，以独立于在其他计算节点执行的处理操作来执行本地处理操作。 每个计算节点还包括构造成通过描述多个注入FIFO的注入FIFO元数据与应用交互的DMA引擎，其中每个注入FIFO可以包含任意数量的消息描述符，以便处理具有固定处理开销的消息，而不管消息的数量 描述符包含在注入FIFO中。

公开(公告)号：US07383490B2

公开(公告)日：2008-06-03

申请号：US11106069

申请日：2005-04-14

申请人： Gheorghe Almasi ,  Matthias Augustin Blumrich ,  Dong Chen ,  Paul Coteus ,  Alan Gara ,  Mark E. Giampapa ,  Philip Heidelberger ,  Dirk I. Hoenicke ,  Sarabjeet Singh ,  Burkhard D. Steinmacher-Burow ,  Todd Takken ,  Pavlos Vranas

发明人： Gheorghe Almasi ,  Matthias Augustin Blumrich ,  Dong Chen ,  Paul Coteus ,  Alan Gara ,  Mark E. Giampapa ,  Philip Heidelberger ,  Dirk I. Hoenicke ,  Sarabjeet Singh ,  Burkhard D. Steinmacher-Burow ,  Todd Takken ,  Pavlos Vranas

IPC分类号： G06F11/00 ,  H03M13/00

CPC分类号： G06F11/1633

摘要： Methods and apparatus perform fault isolation in multiple node computing systems using commutative error detection values for—example, checksums—to identify and to isolate faulty nodes. When information associated with a reproducible portion of a computer program is injected into a network by a node, a commutative error detection value is calculated. At intervals, node fault detection apparatus associated with the multiple node computer system retrieve commutative error detection values associated with the node and stores them in memory. When the computer program is executed again by the multiple node computer system, new commutative error detection values are created and stored in memory. The node fault detection apparatus identifies faulty nodes by comparing commutative error detection values associated with reproducible portions of the application program generated by a particular node from different runs of the application program. Differences in values indicate a possible faulty node.

摘要翻译： 方法和设备使用交换性错误检测值（例如，校验和）识别和隔离故障节点，在多个节点计算系统中执行故障隔离。 当与计算机程序的可再现部分相关联的信息被节点注入到网络中时，计算交换性错误检测值。 每隔一段时间，与多节点计算机系统相关联的节点故障检测装置检索与节点相关联的交换错误检测值并将其存储在存储器中。 当多节点计算机系统再次执行计算机程序时，创建新的交换错误检测值并将其存储在存储器中。 节点故障检测装置通过比较与来自应用程序的不同运行的特定节点生成的应用程序的可再现部分相关联的交换错误检测值来识别故障节点。 值的差异表示可能的故障节点。

公开(公告)号：US20070204112A1

公开(公告)日：2007-08-30

申请号：US11617276

申请日：2006-12-28

申请人： Matthias Blumrich ,  Dong Chen ,  Paul Coteus ,  Alan Gara ,  Mark Giampapa ,  Philip Heidelberger ,  Dirk Hoenicke ,  Martin Ohmacht ,  Burkhard Steinmacher-Burow ,  Todd Takken ,  Pavlos Vranas

发明人： Matthias Blumrich ,  Dong Chen ,  Paul Coteus ,  Alan Gara ,  Mark Giampapa ,  Philip Heidelberger ,  Dirk Hoenicke ,  Martin Ohmacht ,  Burkhard Steinmacher-Burow ,  Todd Takken ,  Pavlos Vranas

IPC分类号： G06F12/14

CPC分类号： G06F12/0862 ,  G06F9/52 ,  G06F2212/6028

摘要： A low latency memory system access is provided in association with a weakly-ordered multiprocessor system. Each processor in the multiprocessor shares resources, and each shared resource has an associated lock within a locking device that provides support for synchronization between the multiple processors in the multiprocessor and the orderly sharing of the resources. A processor only has permission to access a resource when it owns the lock associated with that resource, and an attempt by a processor to own a lock requires only a single load operation, rather than a traditional atomic load followed by store, such that the processor only performs a read operation and the hardware locking device performs a subsequent write operation rather than the processor. A simple prefetching for non-contiguous data structures is also disclosed. A memory line is redefined so that in addition to the normal physical memory data, every line includes a pointer that is large enough to point to any other line in the memory, wherein the pointers to determine which memory line to prefetch rather than some other predictive algorithm. This enables hardware to effectively prefetch memory access patterns that are non-contiguous, but repetitive.

摘要翻译： 与弱有序的多处理器系统相关联地提供低延迟存储器系统访问。 多处理器中的每个处理器共享资源，并且每个共享资源在锁定设备内具有关联的锁，其提供对多处理器中的多个处理器之间的同步的支持以及资源的有序共享。 当处理器拥有与该资源相关联的锁定时，处理器仅具有访问资源的权限，并且处理器拥有锁的尝试仅需要单个加载操作，而不是传统的原子负载后跟存储，使得处理器 只执行读取操作，并且硬件锁定装置执行后续的写入操作而不是处理器。 还公开了用于非连续数据结构的简单预取。 重新定义存储器线，使得除了正常的物理存储器数据之外，每行包括足够大的指针以指向存储器中的任何其他行，其中指针用于确定要预取的存储器行而不是一些其它预测 算法。 这使得硬件能够有效地预取不连续但重复的存储器访问模式。

公开(公告)号：US06190922B1

公开(公告)日：2001-02-20

申请号：US09061294

申请日：1998-04-16

申请人： Dong Chen ,  M. David Shattuck

发明人： Dong Chen ,  M. David Shattuck

IPC分类号： G01N140

CPC分类号： B01J20/28033 ,  B01D15/00 ,  B01J20/26 ,  Y10T436/193333 ,  Y10T436/21 ,  Y10T436/255

摘要： This invention relates generally to a method for the extraction of organic liquid contaminates from a sample. This invention is directed to the ability of hydrophobic extraction material or ribbon tape made of a hydrophobic polymer to facilitate the extraction of liquid organic contaminates from an aqueous sample in contact with an organic non-polar solvent.

摘要翻译： 本发明一般涉及从样品中提取有机液体污染物的方法。 本发明涉及由疏水性聚合物制成的疏水性提取材料或带状带的能力，以便于与有机非极性溶剂接触的水性样品中提取液体有机污染物。