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31.发明授权公开(公告)号：US06868014B1
公开(公告)日：2005-03-15
申请号：US10430604
申请日：2003-05-06
IPC分类号： G11C16/04 , H01L21/28 , H01L29/423 , H01L29/788 , H01L29/792
CPC分类号： H01L29/7923 , H01L21/28282 , H01L29/42324 , H01L29/7887
摘要： A non-volatile memory device includes a semiconductor substrate and a pair of buried bitlines within the substrate. A scaled down dielectric stack is formed over the substrate. The scaled down dielectric stack includes a scaled down top dielectric layer, a scaled down charge trapping dielectric layer and a bottom dielectric layer. A wordline is formed over the dielectric stack. The memory device is operative to be programmed using a reduced wordline operating voltage of less than about +8 Volts, and to be erased using a reduced wordline operating voltage of less than about −6 Volts.
摘要翻译： 非易失性存储器件包括衬底内的半导体衬底和一对掩埋位线。 在衬底上形成按比例缩小的电介质叠层。 按比例缩小的电介质堆叠包括按比例缩小的顶部介电层，按比例缩小的电荷俘获电介质层和底部电介质层。 在介质叠层上形成一条字线。 存储器装置可操作以使用小于约+8伏特的减小的字线工作电压进行编程，并且使用小于约-6伏的减小的字线工作电压来擦除存储器装置。
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公开(公告)号：US08486782B2
公开(公告)日：2013-07-16
申请号：US11615489
申请日：2006-12-22
申请人： Ning Cheng , Fred Cheung , Ashot Melik-Martirosian , Kyunghoon Min , Michael Brennan , Hiroyuki Kinoshita
发明人： Ning Cheng , Fred Cheung , Ashot Melik-Martirosian , Kyunghoon Min , Michael Brennan , Hiroyuki Kinoshita
IPC分类号： H01L21/336
CPC分类号： H01L29/0607 , H01L27/115 , H01L27/11521 , H01L27/11568
摘要： Flash memory devices and methods for fabricating the same are provided. In accordance with an exemplary embodiment of the invention, a method for fabricating a memory device comprises the steps of fabricating a first gate stack and a second gate stack overlying a substrate. A trench is etched into the substrate between the first gate stack and the second gate stack and a first impurity doped region is formed within the substrate underlying the trench. The trench is filled at least partially with a conductive material.
摘要翻译： 提供闪存器件及其制造方法。 根据本发明的示例性实施例，一种用于制造存储器件的方法包括以下步骤：制造覆盖衬底的第一栅极堆叠和第二栅极堆叠。 在第一栅极堆叠和第二栅极堆叠之间蚀刻到衬底中的沟槽，并且在沟槽内的衬底内形成第一杂质掺杂区域。 至少部分地用导电材料填充沟槽。
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33.发明申请公开(公告)号：US20100020607A1
公开(公告)日：2010-01-28
申请号：US12574079
申请日：2009-10-06
CPC分类号： G11C8/10 , G11C16/0416 , G11C16/0491 , G11C16/344 , G11C16/3477
摘要： A method and apparatus are provided for adaptive memory cell overerase compensation. A semiconductor memory device (100) is provided for performing the adaptively compensating erase verify operation (500, 600). The memory device (100) includes at least one word line (402). One or more memory cells (200) and one or more reference cells (406, 408) are connected to the word lines (402), where the one or more reference cells (406, 408) include an erased reference cell (408) connected to each word line (402). The method (500, 600) for adaptive memory cell overerase compensation includes determining an erase verify gate voltage (506, 608) utilizing the erased reference cell(s) (408) and verifying an erase voltage (514) of the memory cells (200) in response to the erase verify gate voltage (512, 614).
摘要翻译： 提供了一种用于自适应存储器单元过渡补偿的方法和装置。 提供一种用于执行自适应补偿擦除验证操作（500,600）的半导体存储器件（100）。 存储装置（100）包括至少一个字线（402）。 一个或多个存储器单元（200）和一个或多个参考单元（406,408）连接到字线（402），其中一个或多个参考单元（406,408）包括连接的擦除参考单元（408） 到每个字线（402）。 用于自适应存储器单元过渡补偿的方法（500,600）包括利用所擦除的参考单元（408）确定擦除验证栅极电压（506,608）并验证存储器单元（200）的擦除电压（514） ）响应于擦除验证栅极电压（512,614）。
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34.发明授权公开(公告)号：US07635627B2
公开(公告)日：2009-12-22
申请号：US11614050
申请日：2006-12-20
IPC分类号： H01L21/336
CPC分类号： H01L27/11568 , H01L21/28273 , H01L21/28282 , H01L27/11521 , H01L29/42328 , H01L29/42332 , H01L29/42344 , H01L29/42348 , H01L29/66825 , H01L29/66833 , H01L29/7883 , H01L29/792
摘要： Methods are provided for fabricating a memory device comprising a dual bit memory cell. The method comprises, in accordance with one embodiment of the invention, forming a gate dielectric layer and a central gate electrode overlying the gate dielectric layer at a surface of a semiconductor substrate. First and second memory storage nodes are formed adjacent the sides of the gate dielectric layer, each of the first and second storage nodes comprising a first dielectric layer and a charge storage layer, the first dielectric layer formed independently of the step of forming the gate dielectric layer. A first control gate is formed overlying the first memory storage node and a second control gate is formed overlying the second memory storage node. A conductive layer is deposited and patterned to form a word line coupled to the central gate electrode, the first control gate, and the second control gate.
摘要翻译： 提供了用于制造包括双位存储单元的存储器件的方法。 该方法包括根据本发明的一个实施例，在半导体衬底的表面上形成覆盖栅极电介质层的栅极电介质层和中心栅电极。 第一和第二存储器存储节点形成在栅极电介质层的侧面附近，第一和第二存储节点中的每一个包括第一介电层和电荷存储层，第一电介质层独立于形成栅极电介质的步骤而形成 层。 第一控制栅极形成在第一存储器存储节点上，并且第二控制栅极形成在第二存储器存储节点上。 导电层被沉积并图案化以形成耦合到中央栅电极，第一控制栅极和第二控制栅极的字线。
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公开(公告)号：US20070237003A1
公开(公告)日：2007-10-11
申请号：US11398415
申请日：2006-04-05
申请人： Ashot Melik-Martirosian , Ed Runnion , Mark Randolph , Meng Ding
发明人： Ashot Melik-Martirosian , Ed Runnion , Mark Randolph , Meng Ding
IPC分类号： G11C16/04
CPC分类号： G11C16/0475 , G11C16/12 , G11C16/344 , G11C16/3445 , G11C16/3454 , G11C16/3459
摘要： A flash memory system configured in accordance with an example embodiment of the invention employs a virtual ground array architecture. During programming operations, target memory cells are biased with a positive source bias voltage to reduce or eliminate leakage current that might otherwise conduct through the target memory cells. A positive source bias voltage may also be applied to target memory cells during verification operations (program verify, soft program verify, erase verify) to reduce or eliminate leakage current that might otherwise introduce errors in the verification operations.
摘要翻译： 根据本发明的示例性实施例配置的闪存系统采用虚拟接地阵列架构。 在编程操作期间，目标存储器单元被偏置为正的源偏置电压，以减少或消除否则可能通过目标存储器单元传导的漏电流。 在验证操作（程序验证，软程序验证，擦除验证）期间，也可以将正源偏置电压施加到目标存储器单元，以减少或消除可能在验证操作中引入错误的泄漏电流。
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36.发明授权公开(公告)号：US06862221B1
公开(公告)日：2005-03-01
申请号：US10459102
申请日：2003-06-11
IPC分类号： G11C16/04 , H01L21/28 , H01L29/423 , H01L29/788 , H01L29/792
CPC分类号： H01L21/28282 , G11C16/0475 , H01L29/42324 , H01L29/7887 , H01L29/7923
摘要： A non-volatile memory device includes a semiconductor substrate and a source and drain within the substrate. A dielectric stack is formed over the substrate. The dielectric stack includes a thin top dielectric layer. A gate electrode is formed over the dielectric stack. The memory device is operative to perform a direct tunneling channel erase operation in which a pair of charge storing cells within a charge storing layer are erased via direct tunneling through the thin top dielectric layer.
摘要翻译： 非易失性存储器件包括半导体衬底和衬底内的源极和漏极。 在衬底上形成电介质叠层。 电介质堆叠包括薄的顶部电介质层。 在电介质叠层上形成栅电极。 存储器装置可操作以执行直接隧道通道擦除操作，其中电荷存储层内的一对电荷存储单元通过经由薄顶介电层的直接隧穿而被擦除。
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37.发明授权Apparatus and method for determining an operating condition of a memory cell based on cycle information 有权基于周期信息确定存储器单元的工作状态的装置和方法公开(公告)号：US08819503B2
公开(公告)日：2014-08-26
申请号：US13044464
申请日：2011-03-09
IPC分类号： G11C29/00
CPC分类号： G06F11/3055 , G06F11/3034 , G11C11/5642 , G11C16/3459 , G11C16/3495 , G11C2211/5621
摘要： Disclosed is an apparatus and method for adjusting a memory parameter in a non-volatile memory circuit. On a trigger event, a parameter is determined in accordance with a circuit characteristic associated with the memory block. The parameter may be a new read level voltage to apply to a page of a memory block, or a program verify level voltage used to program a page of a memory block. On determining the parameter a command is sent to the memory circuit to apply the parameter to the page of the memory block. The method can be triggered by an event such as P/E cycle times and the condition is dynamically adjusted to extend the life of the memory circuit.
摘要翻译： 公开了一种用于调整非易失性存储器电路中的存储器参数的装置和方法。 在触发事件中，根据与存储器块相关联的电路特性来确定参数。 该参数可以是应用于存储器块的页面的新的读取电平电压或用于对存储器块的页面进行编程的程序验证电平电压。 在确定参数时，将命令发送到存储器电路以将参数应用于存储器块的页面。 该方法可以由诸如P / E周期时间的事件来触发，并且动态调整条件以延长存储器电路的寿命。
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38.发明授权Apparatus and method for determining an operating condition of a memory cell based on cycle information 有权基于周期信息确定存储器单元的工作状态的装置和方法公开(公告)号：US08737141B2
公开(公告)日：2014-05-27
申请号：US13177518
申请日：2011-07-06
IPC分类号： G11C7/00
CPC分类号： G06F3/0634 , G06F3/0604 , G06F3/0679 , G06F11/0727 , G06F11/076 , G06F11/079 , G11C16/12 , G11C16/14 , G11C16/349 , G11C16/3495
摘要： Disclosed is an apparatus and method for determining a parameter for programming a non-volatile memory circuit. On receiving write or erase operation a parameter is determined as a function of a circuit characteristic associated with a memory block. An adjusted condition, for example, read or write time, or the standard deviation of voltage thresholds in a distribution of cells, is then determined as a function of the parameter, and a command provided to the memory circuit to use the parameter in the next write or erase operation performed on the memory block. The method can be triggered by an event such as P/E cycle times and the condition is dynamically adjusted to extend the life of the memory circuit.
摘要翻译： 公开了一种用于确定用于编程非易失性存储器电路的参数的装置和方法。 在接收到写入或擦除操作时，根据与存储器块相关联的电路特性确定参数。 然后根据参数确定调整条件，例如读取或写入时间或电池分布中的电压阈值的标准偏差，以及提供给存储器电路以在下一个参数中使用该参数的命令 对存储器块执行的写或擦除操作。 该方法可以由诸如P / E周期时间的事件来触发，并且动态调整条件以延长存储器电路的寿命。
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39.发明授权Dual-bit memory device having isolation material disposed underneath a bit line shared by adjacent dual-bit memory cells 有权具有隔离材料的双位存储器件设置在由相邻的双位存储器单元共享的位线之下公开(公告)号：US08076715B2
公开(公告)日：2011-12-13
申请号：US11616718
申请日：2006-12-27
IPC分类号： H01L29/792
CPC分类号： H01L27/11568 , H01L27/115 , H01L29/66833 , H01L29/7923
摘要： A dual-bit memory device is provided which includes trench isolation material disposed below a bit line that is shared by adjacent memory cells. The dual-bit memory device comprises a substrate, a first memory cell designed to store two bits of information, a second memory cell designed to store two bits of information, and an insulator region. The first memory cell is adjacent to the second memory cell. The first memory cell includes a first buried bit line and a second buried bit line. The first memory cell and the second memory cell share the second buried bit line. The insulator region is disposed in the substrate below the second buried bit line to prevent electrons from flowing between the first memory cell and the second memory cell.
摘要翻译： 提供了一种双位存储器件，其包括布置在由相邻存储器单元共享的位线下方的沟槽隔离材料。 双位存储器件包括衬底，设计用于存储两位信息的第一存储器单元，被设计为存储两位信息的第二存储器单元和绝缘体区域。 第一存储单元与第二存储单元相邻。 第一存储单元包括第一掩埋位线和第二掩埋位线。 第一存储单元和第二存储单元共享第二掩埋位线。 绝缘体区域设置在第二掩埋位线下方的衬底中，以防止电子在第一存储单元和第二存储单元之间流动。
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公开(公告)号：US07630253B2
公开(公告)日：2009-12-08
申请号：US11398415
申请日：2006-04-05
申请人： Ashot Melik-Martirosian , Ed Runnion , Mark Randolph , Meng Ding
发明人： Ashot Melik-Martirosian , Ed Runnion , Mark Randolph , Meng Ding
IPC分类号： G11C16/04
CPC分类号： G11C16/0475 , G11C16/12 , G11C16/344 , G11C16/3445 , G11C16/3454 , G11C16/3459
摘要： A flash memory system configured in accordance with an example embodiment of the invention employs a virtual ground array architecture. During programming operations, target memory cells are biased with a positive source bias voltage to reduce or eliminate leakage current that might otherwise conduct through the target memory cells. A positive source bias voltage may also be applied to target memory cells during verification operations (program verify, soft program verify, erase verify) to reduce or eliminate leakage current that might otherwise introduce errors in the verification operations.
摘要翻译： 根据本发明的示例性实施例配置的闪存系统采用虚拟接地阵列架构。 在编程操作期间，目标存储器单元被偏置为正的源偏置电压，以减少或消除否则可能通过目标存储器单元传导的漏电流。 在验证操作（程序验证，软程序验证，擦除验证）期间，也可以将正源偏置电压施加到目标存储器单元，以减少或消除可能在验证操作中引入错误的泄漏电流。
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