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    USE OF CHLORINE TO FABRICATE TRENCH DIELECTRIC IN INTEGRATED CIRCUITS
    33.
    发明申请
    USE OF CHLORINE TO FABRICATE TRENCH DIELECTRIC IN INTEGRATED CIRCUITS 审中-公开
    在集成电路中使用氯化铁铁素体电介质

    公开(公告)号：US20070128800A1

    公开(公告)日：2007-06-07

    申请号：US11671740

    申请日：2007-02-06

    申请人： Zhong Dong ,  Tai-Peng Lee

    发明人： Zhong Dong ,  Tai-Peng Lee

    IPC分类号： H01L21/336 ,  H01L29/76

    CPC分类号： H01L21/823481 ,  H01L21/76224 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/40114

    摘要： Chlorine is incorporated into pad oxide (110) formed on a silicon substrate (120) before the etch of substrate isolation trenches (134). The chlorine enhances the rounding of the top corners (140C) of the trenches when a silicon oxide liner (150.1) is thermally grown on the trench surfaces. A second silicon oxide liner (150.2) incorporating chlorine is deposited by CVD over the first liner (150.1), and then a third liner (150.3) is thermally grown. The chlorine concentration in the second liner (150.2) and the thickness of the three liners (150.1, 150.2, 150.3) are controlled to improve the corner rounding without consuming too much of the active areas (140).

    摘要翻译： 在衬底隔离沟槽（134）的蚀刻之前，将氯结合到在硅衬底（120）上形成的衬垫氧化物（110）中。 当在沟槽表面上热生长氧化硅衬垫（150.1）时，氯增强了沟槽的顶角（140℃）的倒圆。 通过CVD在第一衬垫（150.1）上沉积掺入氯的第二氧化硅衬垫（150.2），然后热生长第三衬里（150.3）。 控制第二衬套（150.2）中的氯浓度和三个衬垫（150.1,150.2,150.3）的厚度以改善拐角四舍五入，而不消耗太多的有效区域（140）。

    Method of forming dual thickness gate dielectric structures via use of silicon nitride layers
    34.
    发明授权
    Method of forming dual thickness gate dielectric structures via use of silicon nitride layers 失效
    通过使用氮化硅层形成双厚度栅极电介质结构的方法

    公开(公告)号：US06524910B1

    公开(公告)日：2003-02-25

    申请号：US09670329

    申请日：2000-09-27

    申请人： Wenhe Lin ,  Kin Leong Pey ,  Mei Sheng Zhou ,  Zhong Dong ,  Simon Chooi

    发明人： Wenhe Lin ,  Kin Leong Pey ,  Mei Sheng Zhou ,  Zhong Dong ,  Simon Chooi

    IPC分类号： H01L21336

    CPC分类号： H01L21/28185 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/02304 ,  H01L21/28194 ,  H01L21/31662 ,  H01L21/823462 ,  H01L29/513 ,  H01L29/518

    摘要： A process for forming a first group of gate structures, designed to operate at a lower voltage than a simultaneously formed second group of gate structures, has been developed. The process features the thermal growth of a first silicon dioxide gate insulator layer, on a portion of the semiconductor substrate used for the lower voltage gate structures, while simultaneously forming a thicker, second silicon dioxide gate insulator layer on a portion of the semiconductor substrate used for the higher voltage gate structures. The thermal growth of the first, and second silicon dioxide gate insulator layers is accomplished via diffusion of the oxidizing species: through a thick, composite silicon nitride layer, to obtain the thinner, first silicon dioxide gate insulator layer, on a first portion of the semiconductor substrate; and through a thinner, silicon nitride layer, to obtain the thicker, second silicon dioxide gate insulator layer, on a second portion of the semiconductor substrate.

    摘要翻译： 已经开发了一种用于形成第一组栅极结构的工艺，其设计成在比同时形成的第二组栅极结构低的电压下工作。 该方法的特征在于在用于低电压栅极结构的半导体衬底的一部分上的第一二氧化硅栅极绝缘体层的热生长，同时在所使用的半导体衬底的一部分上形成较厚的第二二氧化硅栅极绝缘体层 对于较高电压门结构。 第一和第二二氧化硅栅极绝缘体层的热生长通过氧化物质的扩散来实现：通过厚的复合氮化硅层，以获得较薄的第一二氧化硅栅极绝缘体层，在第一部分 半导体衬底; 并通过较薄的氮化硅层，以在半导体衬底的第二部分上获得较厚的第二二氧化硅栅极绝缘体层。

    Nonvolatile memories with tunnel dielectric with chlorine
    35.
    发明授权
    Nonvolatile memories with tunnel dielectric with chlorine 有权
    带有隧道电介质的非易失性存储器

    公开(公告)号：US07737487B2

    公开(公告)日：2010-06-15

    申请号：US12134834

    申请日：2008-06-06

    申请人： Zhong Dong ,  Barbara Haselden

    发明人： Zhong Dong ,  Barbara Haselden

    IPC分类号： G11C11/34 ,  H01L29/792 ,  H01L21/336

    CPC分类号： H01L21/28282 ,  G11C16/0466 ,  H01L29/513 ,  H01L29/792

    摘要： In a nonvolatile memory cell with charge trapping dielectric (150), the tunnel dielectric (140) includes chlorine adjacent to the charge trapping dielectric but no chlorine (or less chlorine) adjacent to the cell's channel region (120). The chlorine adjacent to the charge trapping dielectric serves to improve the programming and/or erase speed. The low chlorine concentration adjacent to the channel region prevents chlorine from degrading the data retention. Other features are also provided.

    摘要翻译： 在具有电荷捕获电介质（150）的非易失性存储单元中，隧道电介质（140）包括邻近电荷捕获电介质的氯，而与电池的沟道区（120）相邻的氯不含氯（或更少的氯）。 与电荷捕获介质相邻的氯用于改善编程和/或擦除速度。 与通道区相邻的低氯浓度防止氯降解数据保留。 还提供其他功能。

    FABRICATION OF INTEGRATED CIRCUITS WITH ISOLATION TRENCHES
    36.
    发明申请
    FABRICATION OF INTEGRATED CIRCUITS WITH ISOLATION TRENCHES 有权
    集成电路的制造与隔离条

    公开(公告)号：US20100047994A1

    公开(公告)日：2010-02-25

    申请号：US12196067

    申请日：2008-08-21

    申请人： Zhong Dong ,  Ching-Hwa Chen

    发明人： Zhong Dong ,  Ching-Hwa Chen

    IPC分类号： H01L21/764

    CPC分类号： H01L21/76224 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7881 ,  H01L29/792

    摘要： After forming a stack of layers (130, 140, 310) for a transistor or a charge-trapping memory over an active area (110), and before etching isolation trenches (160) in the semiconductor substrate (120) with the stack as a mask, spacers (610) are formed on the stack's sidewalls. The trench etch may include a lateral component, so the top edges of the trenches may be laterally recessed to a position under the spacers or the stack. After the etch, the spacers are removed to facilitate filling the trenches with the dielectric (to eliminate voids at the recessed top edges of the trenches). Other embodiments are also provided.

    摘要翻译： 在有源区（110）上形成用于晶体管或电荷俘获存储器的层叠层（130,140,​​310）之后，以及在将堆叠中的隔离沟槽（160）刻蚀为半导体衬底 掩模，间隔物（610）形成在堆叠的侧壁上。 沟槽蚀刻可以包括侧向部件，因此沟槽的顶部边缘可以横向凹入到间隔件或堆叠下的位置。 在蚀刻之后，去除间隔物以便于用电介质填充沟槽（以消除沟槽凹陷的顶部边缘处的空隙）。 还提供了其他实施例。

    Use of chlorine to fabricate trench dielectric in integrated circuits
    40.
    发明申请
    Use of chlorine to fabricate trench dielectric in integrated circuits 有权
    在集成电路中使用氯来制造沟槽电介质

    公开(公告)号：US20070004136A1

    公开(公告)日：2007-01-04

    申请号：US11174081

    申请日：2005-06-30

    申请人： Zhong Dong ,  Tai-Peng Lee

    发明人： Zhong Dong ,  Tai-Peng Lee

    IPC分类号： H01L21/8238 ,  H01L21/336 ,  H01L29/76

    CPC分类号： H01L21/823481 ,  H01L21/28273 ,  H01L21/76224 ,  H01L27/115 ,  H01L27/11521

    摘要： Chlorine is incorporated into pad oxide (110) formed on a silicon substrate (120) before the etch of substrate isolation trenches (134). The chlorine enhances the rounding of the top corners (140C) of the trenches when a silicon oxide liner (150.1) is thermally grown on the trench surfaces. A second silicon oxide liner (150.2) incorporating chlorine is deposited by CVD over the first liner (150.1), and then a third liner (150.3) is thermally grown. The chlorine concentration in the second liner (150.2) and the thickness of the three liners (150.1, 150.2, 150.3) are controlled to improve the corner rounding without consuming too much of the active areas (140).

    摘要翻译： 在衬底隔离沟槽（134）的蚀刻之前，将氯结合到在硅衬底（120）上形成的衬垫氧化物（110）中。 当在沟槽表面上热生长氧化硅衬垫（150.1）时，氯增强了沟槽的顶角（140℃）的倒圆。 通过CVD在第一衬垫（150.1）上沉积掺入氯的第二氧化硅衬垫（150.2），然后热生长第三衬里（150.3）。 控制第二衬套（150.2）中的氯浓度和三个衬垫（150.1,150.2,150.3）的厚度以改善拐角四舍五入，而不消耗太多的有效区域（140）。