公开(公告)号：US6101322A

公开(公告)日：2000-08-08

申请号：US658538

申请日：1996-06-05

Applicant: Alan L. Goodrum ,  Paul R. Culley ,  Raymond Y. L. Chow ,  Barry S. Basile ,  Richard O. Waldorf ,  Pamela M. Cook ,  Clarence Y. Mar

Inventor： Alan L. Goodrum ,  Paul R. Culley ,  Raymond Y. L. Chow ,  Barry S. Basile ,  Richard O. Waldorf ,  Pamela M. Cook ,  Clarence Y. Mar

IPC: G06F1/26 ,  G06F1/18 ,  G06F1/24 ,  G06F13/40 ,  G06F13/00 ,  G06F1/16

CPC classification number: G06F13/4081

Abstract: A method for powering up a removable circuit card when it is inserted into a card slot of a computer system includes providing power and a clock signal to the circuit card. A communication link is electrically coupled to the circuit card after both the power and the clock signal are provided to the circuit card.

Abstract translation: 将可移除电路卡插入计算机系统的卡插槽时为其供电的方法包括向电路卡提供电力和时钟信号。 在将电源和时钟信号提供给电路卡之后，通信链路电耦合到电路卡。

公开(公告)号：US6098166A

公开(公告)日：2000-08-01

申请号：US58487

申请日：1998-04-10

Applicant: Daniel Lawrence Leibholz ,  Sven Eric Meier ,  James Arthur Farrell ,  Timothy Charles Fischer ,  Derrick Robert Meyer

Inventor： Daniel Lawrence Leibholz ,  Sven Eric Meier ,  James Arthur Farrell ,  Timothy Charles Fischer ,  Derrick Robert Meyer

IPC: G06F9/38 ,  G06F9/312

CPC classification number: G06F9/3838 ,  G06F9/3824 ,  G06F9/3836 ,  G06F9/3842 ,  G06F9/3861

Abstract: A technique for speculatively issuing instructions using an out-of-order processor. A cache miss by a load instruction results in either a reissue of all subsequently issued instructions for an integer instruction stream, or a reissue of only truly dependent instructions for a floating point instruction stream. One version of the technique involves issuing and executing a first instruction, and issuing a second instruction during a speculative time window of the first instruction that occurs after the first instruction is issued. The technique further involves executing the issued second instruction when the first instruction is executed in a first manner, and reissuing the second instruction and executing the reissued second instruction when the first instruction is executed in a second manner that is different than the first manner.

Abstract translation: 一种使用乱序处理器推测发布指令的技术。 通过加载指令的高速缓存未命中导致重新发出所有随后发出的整数指令流指令，或者重新发布浮点指令流的真正依赖指令。 该技术的一个版本涉及发出和执行第一指令，并且在发出第一指令之后发生的第一指令的推测时间窗口期间发出第二指令。 该技术还包括当以第一方式执行第一指令时执行发出的第二指令，并且当以与第一方式不同的第二方式执行第一指令时重新发出第二指令并执行再发行的第二指令。

公开(公告)号：US6098110A

公开(公告)日：2000-08-01

申请号：US777501

申请日：1996-12-30

Applicant: Michael L. Witkowski ,  Gregory T. Chandler ,  Mohammad A. Khan ,  Gary B. Kotzur ,  Dale J. Mayer ,  William J. Walker

Inventor： Michael L. Witkowski ,  Gregory T. Chandler ,  Mohammad A. Khan ,  Gary B. Kotzur ,  Dale J. Mayer ,  William J. Walker

IPC: H04L12/56 ,  G06F15/16 ,  G06F13/38 ,  H04L12/28

CPC classification number: H04L49/351 ,  H04L49/205 ,  H04L49/354 ,  Y10S370/911

Abstract: A network switch including a plurality of first network ports, a plurality of second network ports, a first bus, a second bus and a bridge interface coupled between the first and second buses. The first ports receive and transmit network data according to a first network protocol and the second ports receive and transmit network data according to a second network protocol. The first and second buses operate according to different bus standards. The bridge interface enables data transfer between the first and second buses and thus between the networks operating at different protocols. The switch includes a switch manager that controls the flow of network data and a processor for performing supervisory and control functions. The bridge interface includes receive buffers and transmit buffers assigned to respective ports. During packet data transfer operations across the first bus, the bridge interface emulates a first network port. During packet data transfer operations across the second bus, the bridge interface primarily acts as a slave to the second network ports by storing control lists for execution by the second network ports. This processor is relieved of performing necessary overhead functions associated with the second bus and is thus freed to perform other important switch functions.

Abstract translation: 一种包括多个第一网络端口，多个第二网络端口，第一总线，第二总线和耦合在第一和第二总线之间的桥接口的网络交换机。 第一端口根据第一网络协议接收和发送网络数据，并且第二端口根据第二网络协议接收和发送网络数据。 第一和第二辆公交车根据不同的总线标准运行。 桥接口使得能够在第一和第二总线之间以及因此在以不同协议运行的网络之间进行数据传输。 交换机包括控制网络数据流的交换机管理器和用于执行监控和控制功能的处理器。 桥接口包括分配给相应端口的接收缓冲区和发送缓冲区。 在跨第一总线的分组数据传输操作期间，网桥接口模拟第一个网络端口。 在跨第二总线的分组数据传输操作期间，网桥接口主要通过存储用于由第二网络端口执行的控制列表而作为第二网络端口的从设备。 该处理器不需要执行与第二总线相关联的必要开销功能，因此可以释放以执行其他重要的开关功能。

公开(公告)号：US6097939A

公开(公告)日：2000-08-01

申请号：US891556

申请日：1997-07-11

Applicant: Pamela J. Jacobs

Inventor： Pamela J. Jacobs

IPC: H04K1/00 ,  H04M1/66 ,  H04M3/16

CPC classification number: H04Q3/0045 ,  H04Q3/0025

Abstract: A method and apparatus for allowing an Authentication Center (AC) in a cellular telephone system to store and access event a predefined number of maintenance data events on a per-MIN/ESN basis.

Abstract translation: 一种用于允许蜂窝电话系统中的认证中心（AC）在每MIN / ESN基础上存储和访问预定数量的维护数据事件的方法和装置。

公开(公告)号：US6094700A

公开(公告)日：2000-07-25

申请号：US42333

申请日：1998-03-13

Applicant: Todd Deschepper ,  David J. DeLisle ,  Russ Wunderlich

Inventor： Todd Deschepper ,  David J. DeLisle ,  Russ Wunderlich

IPC: G06F13/40 ,  G06F13/00

CPC classification number: G06F13/405

Abstract: A computer system includes an I/O controller and a bridge logic device which transmit status data via a serial bus. The I/O controller comprises an embedded controller, a memory device, and a serial bus interface including a transceiver, a transmit register, and a receiver register. The bridge logic also includes a serial bus interface with a transceiver, a transmit register, and a receiver register. Data is transmitted from the transmit register of one device to the receive register of the other device. Although the serial bus protocol limits data transfers to eight-bit segments, the I/O controller and bridge logic transmit up to twenty-four different variables by encoding each transmitted byte into a data frame that includes a two-bit frame identifier and a six-bit data field. Further, one of the data frames transmitted by the I/O controller includes an acknowledge bit to indicate when a previous frame has been received from the bridge logic. The bridge logic only transmits new data if the I/O controller toggles the acknowledge bit and transmits the frame containing the toggled acknowledge bit to the bridge logic. The acknowledge bit prevents the South Bridge from overwriting previously transmitted data that has not yet been read from the receive register in the I/O controller.

Abstract translation: 计算机系统包括I / O控制器和经由串行总线发送状态数据的桥逻辑器件。 I / O控制器包括嵌入式控制器，存储器件以及包括收发器，发送寄存器和接收器寄存器的串行总线接口。 桥逻辑还包括具有收发器的串行总线接口，发送寄存器和接收器寄存器。 数据从一个设备的发送寄存器发送到另一个设备的接收寄存器。 虽然串行总线协议将数据传输限制到八位段，但是I / O控制器和桥逻辑通过将每个发送的字节编码到包括两位帧标识符和六位数据帧的数据帧中来传输多达二十四个不同的变量 位数据字段。 此外，由I / O控制器发送的数据帧之一包括确认位，以指示从桥逻辑接收到先前帧的时间。 如果I / O控制器切换应答位，则桥逻辑仅传输新数据，并将包含切换应答位的帧发送到桥逻辑。 应答位可防止南桥覆盖从I / O控制器中的接收寄存器尚未读取的先前传输的数据。

公开(公告)号：US6092189A

公开(公告)日：2000-07-18

申请号：US70589

申请日：1998-04-30

Applicant: Jerald C. Fisher ,  Lien Dai Nguyen ,  James Young ,  Gunnar P. Seaburg ,  Galen W. Hedlund ,  Richard S. Katz

Inventor： Jerald C. Fisher ,  Lien Dai Nguyen ,  James Young ,  Gunnar P. Seaburg ,  Galen W. Hedlund ,  Richard S. Katz

IPC: G06F1/00 ,  G06F9/44 ,  G06F9/445 ,  G06F9/45 ,  G06F11/00

CPC classification number: G06F8/71 ,  G06F2211/1097

Abstract: A process for the mass production of computers where software is automatically installed according to configure-to-order requirements. Additionally, the process captures the as-built hardware and software components of each computer for the vendor service and support program. Furthermore, the process provides a software installation environment which is secure from any undetectable alteration and offers control and auditing of subcontractors who produce systems according to manufacturer's specifications. Finally, the process automates the tracking and reporting of royalty payments to the appropriate recipient.

Abstract translation: 大规模生产计算机的过程，其中软件根据配置到订单的要求自动安装。 此外，该过程捕获供应商服务和支持程序的每台计算机的建立的硬件和软件组件。 此外，该过程提供了一个安全的软件安装环境，无法检测到任何变更，并根据制造商的规范提供对生产系统的分包商的控制和审核。 最后，该过程自动跟踪和报告给适当收件人的特许权使用费。

公开(公告)号：US6091608A

公开(公告)日：2000-07-18

申请号：US385509

申请日：1995-02-08

Applicant: Kurt Michael Thaller ,  Eugene Smith

Inventor： Kurt Michael Thaller ,  Eugene Smith

IPC: H05K1/02 ,  H05K1/14 ,  H05K3/22 ,  H05K3/34 ,  H05K1/11 ,  H01R23/68

CPC classification number: H05K1/141 ,  H05K3/225 ,  H05K1/023 ,  H05K2201/096 ,  H05K2201/10689 ,  H05K2201/10704 ,  H05K3/3447 ,  Y10T29/49126 ,  Y10T29/49139

Abstract: A method and apparatus for attaching a set of components to a printed circuit board is presented. A second board includes the set of components to be attached to the printed circuit board. The second board attaches directly to the printed circuit board by attaching to pins of a through hole device, such as an application specific integrated circuit. The through hole device is mounted on one side of the printed circuit board. The through hole device includes pins which protrude to the other side of the printed circuit board. The second board attaches to the protruding pins on the other side of the printed circuit board.

Abstract translation: 本发明提供一种用于将一组部件附着到印刷电路板上的方法和装置。 第二板包括要附接到印刷电路板的组件组。 第二板通过连接到诸如专用集成电路的通孔装置的引脚直接附接到印刷电路板。 通孔装置安装在印刷电路板的一侧。 通孔装置包括突出到印刷电路板的另一侧的销。 第二板连接到印刷电路板另一侧的突出销。

公开(公告)号：US6086476A

公开(公告)日：2000-07-11

申请号：US127565

申请日：1998-07-31

Applicant: David Paquin ,  David Deis ,  Lowell Good

Inventor： David Paquin ,  David Deis ,  Lowell Good

IPC: G06F1/20 ,  H05K7/20 ,  H05K5/00

CPC classification number: H05K7/20727 ,  G06F1/20

Abstract: A system for cooling a heat-producing component in a computer system includes a conduit or plenum and a fan assembly. The fan assembly may be supported by the conduit. An air stream directing and acoustic shielding member is disposed in the conduit to prevent or reduce transmission of acoustic noise during operation of the fan assembly to a region outside the computer console. The shield member may be made of an open-cell foam or other sound deadening or reflecting material. A secondary conduit is provided for recirculating a portion of the internal air within the computer chassis. The internal air stream may be joined and mixed with the air stream from outside the chassis to provide both fresh air and recirculation cooling.

Abstract translation: 用于冷却计算机系统中的发热部件的系统包括导管或增压室和风扇组件。 风扇组件可以由导管支撑。 气流引导和声屏蔽构件设置在导管中以防止或减少风扇组件操作期间声学噪声的传播到计算机控制台外部的区域。 屏蔽构件可以由开孔泡沫或其它消声或反射材料制成。 设置有用于使计算机机箱内部空气的一部分再循环的次级导管。 内部空气流可以与底盘外部的空气流接合并混合，以提供新鲜空气和再循环冷却。

公开(公告)号：US6085318A

公开(公告)日：2000-07-04

申请号：US957471

申请日：1997-10-24

Applicant: Kerry B. Vander Kamp ,  Roberta W. Hensley ,  Curtis R. Jones

Inventor： Kerry B. Vander Kamp ,  Roberta W. Hensley ,  Curtis R. Jones

IPC: G06F9/445

CPC classification number: G06F9/4406

Abstract: A computer system capable of booting currently manufacturable CD-ROMs or tapes without altering the ISO standard or requiring special, customized software to perform this function. A CD-ROM developed for booting according to the present invention contains a boot record as defined by the ISO but located at the end of the defined system area. The operating code of the computer scans for a boot record starting at the beginning sector of the CD-ROM and ending at either a default number or the volume descriptor terminator. The floppy disk boot images are contained at the end of the primary volume space and incorporated in the primary volume space, not external to the primary volume space as in the ISO standard. Boot code contained in the boot record determines the size of the volume, and the proper floppy image to be used and then the actual location of the floppy image. Booting of the system then commences using the floppy image.

Abstract translation: 一种能够启动当前可制造的CD-ROM或磁带而不改变ISO标准或需要特殊的定制软件来执行此功能的计算机系统。 根据本发明开发用于引导的CD-ROM包含由ISO定义但位于所定义的系统区域的末尾的引导记录。 计算机的操作代码扫描从CD-ROM的开始部分开始并以默认数字或卷描述符终止符结尾的引导记录。 软盘引导映像包含在主卷空间的末尾，并且被包含在主卷空间中，而不是ISO标准中的主卷空间外部。 引导记录中包含的引导代码决定了卷的大小，以及要使用的正确的软盘映像，然后确定软盘映像的实际位置。 系统的引导然后开始使用软盘映像。

公开(公告)号：US6081887A

公开(公告)日：2000-06-27

申请号：US191869

申请日：1998-11-12

Applicant: Simon C. Steely, Jr. ,  Edward J. McLellan ,  Joel S. Emer

Inventor： Simon C. Steely, Jr. ,  Edward J. McLellan ,  Joel S. Emer

IPC: G06F9/38 ,  G06F9/32

CPC classification number: G06F9/3844

Abstract: A technique for predicting the result of a conditional branch instruction for use with a processor having instruction pipeline. A stored predictor is connected to the front end of the pipeline and is trained from a truth based predictor connected to the back end of the pipeline. The stored predictor is accessible in one instruction cycle, and therefore provides minimum predictor latency. Update latency is minimized by storing multiple predictions in the front end stored predictor which are indexed by an index counter. The multiple predictions, as provided by the back end, are indexed by the index counter to select a particular one as current prediction on a given instruction pipeline cycle. The front end stored predictor also passes along to the back end predictor, such as through the instruction pipeline, a position value used to generate the predictions. This further structure accommodates ghost branch instructions that turn out to be flushed out of the pipeline when it must be backed up. As a result, the front end always provides an accurate prediction with minimum update latency.

Abstract translation: 一种用于预测与具有指令流水线的处理器一起使用的条件转移指令的结果的技术。 存储的预测器连接到管道的前端，并且从连接到管道后端的基于真实的预测器训练。 存储的预测器可以在一个指令周期中访问，因此提供最小预测器延迟。 通过将多个预测存储在由索引计数器索引的前端存储的预测器中来最小化更新延迟。 由后端提供的多个预测由索引计数器索引，以选择特定的预测作为给定指令流水线周期上的当前预测。 前端存储的预测器还将传递到后端预测器，例如通过指令流水线，用于产生预测的位置值。 这种进一步的结构可以容纳重影分支指令，当它必须被备份时，这些指令将被清除流出管道。 因此，前端总是以最小的更新延迟提供准确的预测。