公开(公告)号：US20080126763A1

公开(公告)日：2008-05-29

申请号：US11469919

申请日：2006-09-05

申请人： John R. Ehrman ,  Mike S. Fulton ,  Dan F. Greiner

发明人： John R. Ehrman ,  Mike S. Fulton ,  Dan F. Greiner

IPC分类号： G06F9/318

CPC分类号： G06F9/30174 ,  G06F9/30018 ,  G06F9/30098 ,  G06F9/30145 ,  G06F9/30185

摘要： A method, article, and system for providing an effective implementation of assembler language translate-n-to-n instructions implemented on 21, 31, and 64-bit architectures, while maintaining backward compatibility with existing systems. The enhanced Extended-Translation Facility 2 (ETF2) instruction set introduces a new operand in an unused field (M3) that facilitates a change in the original instruction format and its intended function. With the ETF2-Enhancement Facility installed, a value of zeros in the M3 field indicates that instruction operation is to continue as originally defined. When a nonzero value is coded in the M3 field a new function is carried out. The assembler accommodates the changes by making the new M3 field optional when coding the instructions. If the M3 field is not coded, the assembler defaults to providing zeros in the M3 field (as found in the original instruction format), and backward compatible operation is provided.

摘要翻译： 一种用于提供在21,31和64位架构上实现的汇编语言translate-n-to-n指令的有效实现的方法，文章和系统，同时保持与现有系统的向后兼容性。 增强型扩展转换工具2（ETF2）指令集在未使用的字段（M 3 3 ）中引入了一个新操作数，这有助于原始指令格式及其预期功能的改变。 在安装了ETF2-Enhancement Facility的情况下，M＆lt; 3＆lt; 3＆gt;字段中的零值表示指令操作将按原来定义继续。 当非零值被编码在M＆lt; 3＆lt; 3＆gt;字段中时，执行新的功能。 当对指令进行编码时，通过使新的“3”字段可选，汇编器适应这些更改。 如果M 3字段未被编码，则汇编器默认在M SUB 3字段中提供零（如原始指令格式所示），并且提供向后兼容操作 。

公开(公告)号：US20080114970A1

公开(公告)日：2008-05-15

申请号：US11602277

申请日：2006-11-15

申请人： Osvaldo M. Colavin

发明人： Osvaldo M. Colavin

IPC分类号： G06F9/318

CPC分类号： G06F9/325 ,  G06F9/30076 ,  G06F9/3013 ,  G06F9/30138 ,  G06F9/30189 ,  G06F9/3824 ,  G06F9/3826 ,  G06F9/3838 ,  G06F9/384 ,  G06F9/3853 ,  G06F9/3867 ,  G06F9/3887

摘要： An improved superscalar processor. The processor includes multiple lanes, allowing multiple instructions in a bundle to be executed in parallel. In vector mode, the parallel lanes may be used to execute multiple instances of a bundle, representing multiple iterations of the bundle in a vector run. Scheduling logic determines whether, for each bundle, multiple instances can be executed in parallel. If multiple instances can be executed in parallel, coupling circuitry couples an instance of the bundle from one lane into one or more other lanes. In each lane, register addresses are renamed to ensure proper execution of the bundles in the vector run. Additionally, the processor may include a register bank separate from the architectural register file. Renaming logic can generate addresses to this separate register bank that are longer than used to address architectural registers, allowing longer vectors and more efficient processor operation.

摘要翻译： 改进的超标量处理器 处理器包括多个通道，允许并行执行捆绑中的多个指令。 在向量模式中，并行通道可用于执行捆绑的多个实例，表示向量运行中捆绑的多次迭代。 调度逻辑决定了对于每个bundle，是否可以并行执行多个实例。 如果并行执行多个实例，耦合电路将一个实体的捆绑从一个通道耦合到一个或多个其他通道。 在每个通道中，重命名寄存器地址以确保在向量运行中正确执行捆绑。 此外，处理器可以包括与架构寄存器文件分离的寄存器组。 重命名逻辑可以为这个单独的寄存器组生成比用于寻址架构寄存器更长的地址，允许更长的向量和更高效的处理器操作。

公开(公告)号：US20080052498A1

公开(公告)日：2008-02-28

申请号：US11842260

申请日：2007-08-21

申请人： Kevin Alexander Stoodley ,  Mark Graham Stoodley

发明人： Kevin Alexander Stoodley ,  Mark Graham Stoodley

IPC分类号： G06F9/318

CPC分类号： G06F9/3851

摘要： A code region forming part of a computer program is modified during execution of the computer program by a plurality of threads. In one aspect, identical modification instructions are provided to each thread for modifying a site in the code region having a desirable idempotent atomic modification, and the modification instructions direct each thread to make the desirable idempotent atomic modification. In another aspect, a thread is selected to modify the code region, each thread other than the selected thread is directed to execute an alternative execution path that generates output identical to the output of the code region after the code region has been modified, and, responsive to directing each thread other than the selected thread, the selected thread is directed to modify the code region.

摘要翻译： 构成计算机程序的一部分的代码区域被多个线程执行计算机程序期间被修改。 在一个方面，向每个线程提供相同的修改指令，用于修改具有所需幂等原子修改的代码区域中的站点，并且修改指令指示每个线程进行所需的等幂原子修改。 在另一方面，选择线程来修改代码区域，除了所选线程之外的每个线程被引导以执行在代码区域被修改之后产生与代码区域的输出相同的输出的替代执行路径， 响应于指导除所选线程之外的每个线程，所选线程被引导以修改代码区域。

公开(公告)号：US06988182B2

公开(公告)日：2006-01-17

申请号：US10075080

申请日：2002-02-13

申请人： Michael E. Teachman ,  Martin A. Hancock ,  Catherine A. Duncan ,  Benedikt T. Huber

发明人： Michael E. Teachman ,  Martin A. Hancock ,  Catherine A. Duncan ,  Benedikt T. Huber

IPC分类号： G06F9/318

CPC分类号： G06F9/4401 ,  G06F8/65

摘要： An improved method of upgrading the firmware of an electronic device is disclosed. The method is executed over a communications link. The method includes compression of a portion of the new firmware, but does not require the device to have any pre-existing decompression algorithms built into it. A system and device capable of executing the method is also disclosed.

公开(公告)号：US20050289325A1

公开(公告)日：2005-12-29

申请号：US11215862

申请日：2005-08-30

申请人： Gad Sheaffer

发明人： Gad Sheaffer

IPC分类号： G06F9/30 ,  G06F9/318 ,  G06F15/00

CPC分类号： G06F9/30076 ,  G06F9/30174 ,  G06F9/30181 ,  G06F9/30185

摘要： Instruction set extension using operand bearing no-operation (NOP) or other instructions. In one embodiment, an apparatus can execute a first instruction with an operand associated with a second instruction. The apparatus includes a decoder to identify an operand associated with the second instruction as being designated for the first instruction. An execution unit executes an operation indicated by the first instruction to operate on the operand associated with the second instruction. The second instruction may occur before or after the first instruction in the program sequence.

公开(公告)号：US20050283586A1

公开(公告)日：2005-12-22

申请号：US10876092

申请日：2004-06-22

申请人： Sanjoy Mondal ,  Venkateswara Madduri

发明人： Sanjoy Mondal ,  Venkateswara Madduri

IPC分类号： G06F9/318 ,  G06F9/455 ,  G06F15/00

CPC分类号： G06F11/3664 ,  G06F9/3017 ,  G06F9/45558 ,  G06F2009/45591

摘要： A virtual machine extension (VMX) architecture. More particularly, embodiments of the invention relate to a method and apparatus to enable single stepping of a guest application within a microprocessor or group of processing elements.

摘要翻译： 虚拟机扩展（VMX）架构。 更具体地，本发明的实施例涉及一种在微处理器或处理元件组内实现客户应用程序的单步执行的方法和装置。

公开(公告)号：US20050273581A1

公开(公告)日：2005-12-08

申请号：US11204555

申请日：2005-08-15

申请人： Jeffrey Arnold ,  Gareld Banta ,  Scott Johnson ,  Albert Wang

发明人： Jeffrey Arnold ,  Gareld Banta ,  Scott Johnson ,  Albert Wang

IPC分类号： G06F7/38 ,  G06F9/00 ,  G06F9/30 ,  G06F9/302 ,  G06F9/312 ,  G06F9/318 ,  G06F9/38 ,  G06F9/45 ,  G06F12/00 ,  G06F15/00 ,  G06F15/76

CPC分类号： G06F9/383 ,  G06F9/30043 ,  G06F9/3816

摘要： A processing system with reconfigurable instruction extensions includes a processor, programmable logic, a register file, and a load/store module. The processor executes a computer program comprising a set of computational instructions and at least one instruction extension. The programmable logic receives configuration information to configure the programmable logic for the instruction extension and executes the instruction extension. The register file is coupled to the programmable logic and stores data. The load/store module transfers the data directly between the register file and a system memory.

摘要翻译： 具有可重新配置的指令扩展的处理系统包括处理器，可编程逻辑，寄存器文件和加载/存储模块。 处理器执行包括一组计算指令和至少一个指令扩展的计算机程序。 可编程逻辑接收配置信息以配置指令扩展的可编程逻辑并执行指令扩展。 寄存器文件耦合到可编程逻辑并存储数据。 加载/存储模块直接在寄存器文件和系统存储器之间传输数据。

公开(公告)号：US20050267996A1

公开(公告)日：2005-12-01

申请号：US11096183

申请日：2005-03-30

申请人： James O'Connor ,  Marc Tremblay

发明人： James O'Connor ,  Marc Tremblay

IPC分类号： G06F9/34 ,  G06F3/00 ,  G06F9/00 ,  G06F9/30 ,  G06F9/318 ,  G06F9/345 ,  G06F9/40 ,  G06F9/42 ,  G06F9/44 ,  G06F9/455 ,  G06F11/00 ,  G06F12/08 ,  G06F15/78

CPC分类号： G06F15/7846 ,  G06F9/264 ,  G06F9/30021 ,  G06F9/30134 ,  G06F9/30145 ,  G06F9/30167 ,  G06F9/3017 ,  G06F9/30174 ,  G06F9/345 ,  G06F9/3802 ,  G06F9/449 ,  G06F9/45504 ,  G06F9/45516 ,  G06F12/0875 ,  G06F2212/451

摘要： A memory architecture in accordance with an embodiment of the present invention improves the speed of method invocation. Specifically, method frames of method calls are stored in two different memory circuits. The first memory circuit stores the execution environment of each method call, and the second memory circuit stores parameters, variables or operands of the method calls. In one embodiment the execution environment includes a return program counter, a return frame, a return constant pool, a current method vector, and a current monitor address. In some embodiments, the memory circuits are stacks; therefore, the stack management unit to cache can be used to cache either or both memory circuits. The stack management unit can include a stack cache to accelerate data transfers between a stack-based computing system and the stacks. In one embodiment, the stack management unit includes a stack cache, a dribble manager unit, and a stack control unit. The dribble manager unit includes a fill control unit and a spill control unit. Since the vast majority of memory accesses to the stack occur at or near the top of the stack, the dribble manager unit maintains the top portion of the stack in the stack cache. When the stack-based computing system is popping data off of the stack and a fill condition occurs, the fill control unit transfer data from the stack to the bottom of the stack cache to maintain the top portion of the stack in the stack cache. Typically, a fill condition occurs as the stack cache becomes empty and a spill condition occurs as the stack cache becomes full.

公开(公告)号：US20050259777A1

公开(公告)日：2005-11-24

申请号：US10849749

申请日：2004-05-19

申请人： George Claseman

发明人： George Claseman

IPC分类号： G06F9/30 ,  G06F9/318 ,  G06F12/06 ,  G11C19/00

CPC分类号： G06F9/3012 ,  G06F9/30138 ,  G06F12/0623

摘要： A microprocessor includes a plurality of blocks of registers, each block of registers having at least two registers. The microprocessor further includes a location register for selectively characterizing at least one of the blocks as a specified block of registers, and a control register for selecting at least one operation for the indicated block of registers. In one example of the invention, the control and location registers are two of the registers specified by the IEEE 802.3 standard.

摘要翻译： 微处理器包括多个寄存器块，每个寄存器块具有至少两个寄存器。 微处理器还包括位置寄存器，用于选择性地将块中的至少一个表征为指定的寄存器块;以及控制寄存器，用于为指示的寄存器块选择至少一个操作。 在本发明的一个示例中，控制和位置寄存器是IEEE 802.3标准规定的两个寄存器。

公开(公告)号：US20050256920A1

公开(公告)日：2005-11-17

申请号：US11130472

申请日：2005-05-16

申请人： Thomas Crispin ,  G. Henry ,  Terry Parks

发明人： Thomas Crispin ,  G. Henry ,  Terry Parks

IPC分类号： G06F7/38 ,  G06F9/302 ,  G06F9/318

CPC分类号： G06F7/728 ,  G06F9/3001 ,  G06F9/3017 ,  G06F9/30174

摘要： A technique is provided for performing modular multiplication. In one embodiment, an apparatus in a microprocessor is provided for accomplishing modular multiplication operations. The apparatus includes translation logic and execution logic. The translation logic receives a Montgomery multiplication instruction from a source therefrom, where the Montgomery multiplication instruction prescribes generation of a Montgomery product. The translation logic translates the Montgomery multiplication instruction into a sequence of micro instructions specifying sub-operations required to accomplish generation of the Montgomery product. The execution logic is operatively coupled to the translation logic. The execution logic receives the sequence of micro instructions, and performs the sub-operations to generate the Montgomery product.

摘要翻译： 提供了一种用于执行模乘法的技术。 在一个实施例中，微处理器中的装置被提供用于完成模数乘法运算。 该装置包括翻译逻辑和执行逻辑。 翻译逻辑从其源头接收蒙哥马利乘法指令，其中蒙哥马利乘法指令规定了蒙哥马利产品的生成。 翻译逻辑将蒙哥马利乘法指令转换为指定完成蒙哥马利产品生成所需的子操作的微指令序列。 执行逻辑可操作地耦合到翻译逻辑。 执行逻辑接收微指令序列，并执行子操作以生成蒙哥马利产品。