摘要:
A system and method for adding reconfigurable computational instructions to a reduced instruction set computer. A computer program contains instruction extensions not native to the instruction set of the processor core and is loaded into an instruction memory accessible by the processor core of the computer. The computer program is then detected for containing the instruction extension. The programmable logic device is then configured to execute the instruction extension. The programmable logic device then executes the instruction extension for use by the processor core in processing the computer program.
摘要:
A processing system with reconfigurable instruction extensions includes a processor, programmable logic, a register file, and a load/store module. The processor executes a computer program comprising a set of computational instructions and at least one instruction extension. The programmable logic receives configuration information to configure the programmable logic for the instruction extension and executes the instruction extension. The register file is coupled to the programmable logic and stores data. The load/store module transfers the data directly between the register file and a system memory.
摘要:
A video processing system with reconfigurable instructions includes a processor, a first register file in the processor, an extension adapter, programmable logic, a second register file coupled to the programmable logic, and a load/store module. The processor executes a video application that contains an instruction extension not native to the instruction set of the processor. The extension adapter detects the instruction extension in the video application. The programmable logic device is configured to execute the instruction extension. The programmable logic device then executes the instruction extension. The load/store module transfers data between the first register file and the second register file, and transfers data directly between the second register file and a system memory for use by the processor in processing the video application.
摘要:
A system and method provide unaligned load/store functionality for a processor that supports only aligned load/store instructions. An exemplary embodiment includes an extension adapter including registers for storing data and load/store buffers for realigning data. A processor executes aligned load/store instructions that transfer data in multiples of bytes. Instructions are included for transferring data between memory and the load/store buffers, initializing and transferring data, initializing and transferring data in numbers of bits, advancing or offsetting a data pointer, and for flushing the load/store buffers. In a preferred embodiment, the extension adapter comprises a wide register file for buffering full words of data, load/store buffers formed from multiple single-bit registers for buffering data bits and streaming data for use by the processor, and address generators for pointing to data or memory addresses.
摘要:
An image processing system includes at least two, complementary, angle sensitive pixel (ASP) structures, having a spatial frequency domain ASP output including a background output and a plurality of ASP response outputs, in response to an optical input; an ASP response output subtractor component, which functions to suppress the background output and perform a subtraction of at least two of the ASP response outputs; and a processing component that can process the subtracted spatial frequency domain ASP response outputs. An optical domain image processing method includes the steps of providing at least two, complementary, angle sensitive pixel (ASP) structures; obtaining a spatial frequency domain ASP output including a plurality of complementary ASP response outputs, in response to an optical input; performing a wavelet-like transform of the ASP response outputs in the optical domain prior to performing any operation in a digital domain; and obtaining a desired output of the optical input.
摘要:
Manufacturing process planning is usually considered as not intuitive for non-expert user. This is because a user needs to deal with processes, describing a work to be done, and other abstract concepts that are loosely related to the real world. Accordingly, a method and corresponding apparatus according to an embodiment of the present invention are provided to describe a work to be done in response to a user interacting with a three-dimensional representation of one or more parts that form a product and to provide the user with feedback in the form of a graphical representation of the work to be done. This approach is very intuitive as it is close to how a user would, for example, in a real world, decompose a product into sub-assemblies that essentially results into a definition of a manufacturing process of the product.
摘要:
An on-chip inductor device for Integrated Circuits utilizes coils on a plurality of metal layers of the IC with electrical connectors between the coils and a magnetic core for the inductor of stacked vias running between the coils. The magnetic core is made from a series of stacked vias which are deposited between each metal layer of the IC having a coil. The magnetic core desirably includes an array of magnetic bars comprising the magnetic core. The via material of the magnetic core may be both magnetic and electrically conductive. The magnetic and electrically conductive via material may also be used for the planar coil electrical connectors or other electrically conductive parts of the IC, or both, thereby lessening fabrication steps. Films of magnetic material may be formed at the ends of the inductor to provide a closed magnetic circuit for the inductor. A high Q factor inductor of small (e.g., transistor) size is thus obtained. The materials and processes which enable the on-chip inductor device are compatible with ordinary IC fabrication methods.
摘要:
A new general method for building hybrid processors achieves higher performance in applications by allowing more powerful, tightly-coupled instruction set extensions to be implemented in reconfigurable logic. New instructions set configurations can be discovered and designed by automatic and semi-automatic methods. Improved reconfigurable execution units support deep pipelining, addition of additional registers and register files, compound instructions with many source and destination registers and wide data paths. New interface methods allow lower latency, higher bandwidth connections between hybrid processors and other logic.
摘要:
A pipette for use with a pipette tip to aspirate and dispense a quantity of liquid, comprising a housing, a pipette tip mounting shaft extending from the housing to receive a pipette tip, a pipette tip ejector mechanism for ejecting the pipette tip from the mounting shaft, energy storage means, means for storing energy in the energy storage means and means for releasing energy from the energy storage means to assist the tip ejector mechanism in the ejecting of the pipette tip from the mounting shaft.