公开(公告)号：US08161266B2

公开(公告)日：2012-04-17

申请号：US12341250

申请日：2008-12-22

Applicant: Osvaldo M. Colavin

Inventor： Osvaldo M. Colavin

IPC: G06F9/34

CPC classification number: G06F9/325 ,  G06F9/30076 ,  G06F9/3013 ,  G06F9/30138 ,  G06F9/30189 ,  G06F9/3824 ,  G06F9/3826 ,  G06F9/3838 ,  G06F9/384 ,  G06F9/3853 ,  G06F9/3867 ,  G06F9/3887

Abstract: An improved superscalar processor. The processor includes multiple lanes, allowing multiple instructions in a bundle to be executed in parallel. In vector mode, the parallel lanes may be used to execute multiple instances of a bundle, representing multiple iterations of the bundle in a vector run. Scheduling logic determines whether, for each bundle, multiple instances can be executed in parallel. If multiple instances can be executed in parallel, coupling circuitry couples an instance of the bundle from one lane into one or more other lanes. In each lane, register addresses are renamed to ensure proper execution of the bundles in the vector run. Additionally, the processor may include a register bank separate from the architectural register file. Renaming logic can generate addresses to this separate register bank that are longer than used to address architectural registers, allowing longer vectors and more efficient processor operation.

Abstract translation: 改进的超标量处理器 处理器包括多个通道，允许并行执行捆绑中的多个指令。 在向量模式中，并行通道可用于执行捆绑的多个实例，表示向量运行中捆绑的多次迭代。 调度逻辑决定了对于每个bundle，是否可以并行执行多个实例。 如果并行执行多个实例，耦合电路将一个实体的捆绑从一个通道耦合到一个或多个其他通道。 在每个通道中，重命名寄存器地址以确保在向量运行中正确执行捆绑。 此外，处理器可以包括与架构寄存器文件分离的寄存器组。 重命名逻辑可以为这个单独的寄存器组生成比用于寻址架构寄存器更长的地址，允许更长的向量和更高效的处理器操作。

公开(公告)号：US20080114970A1

公开(公告)日：2008-05-15

申请号：US11602277

申请日：2006-11-15

Applicant: Osvaldo M. Colavin

Inventor： Osvaldo M. Colavin

IPC: G06F9/318

CPC classification number: G06F9/325 ,  G06F9/30076 ,  G06F9/3013 ,  G06F9/30138 ,  G06F9/30189 ,  G06F9/3824 ,  G06F9/3826 ,  G06F9/3838 ,  G06F9/384 ,  G06F9/3853 ,  G06F9/3867 ,  G06F9/3887

Abstract: An improved superscalar processor. The processor includes multiple lanes, allowing multiple instructions in a bundle to be executed in parallel. In vector mode, the parallel lanes may be used to execute multiple instances of a bundle, representing multiple iterations of the bundle in a vector run. Scheduling logic determines whether, for each bundle, multiple instances can be executed in parallel. If multiple instances can be executed in parallel, coupling circuitry couples an instance of the bundle from one lane into one or more other lanes. In each lane, register addresses are renamed to ensure proper execution of the bundles in the vector run. Additionally, the processor may include a register bank separate from the architectural register file. Renaming logic can generate addresses to this separate register bank that are longer than used to address architectural registers, allowing longer vectors and more efficient processor operation.

Abstract translation: 改进的超标量处理器 处理器包括多个通道，允许并行执行捆绑中的多个指令。 在向量模式中，并行通道可用于执行捆绑的多个实例，表示向量运行中捆绑的多次迭代。 调度逻辑决定了对于每个bundle，是否可以并行执行多个实例。 如果并行执行多个实例，耦合电路将一个实体的捆绑从一个通道耦合到一个或多个其他通道。 在每个通道中，重命名寄存器地址以确保在向量运行中正确执行捆绑。 此外，处理器可以包括与架构寄存器文件分离的寄存器组。 重命名逻辑可以为这个单独的寄存器组生成比用于寻址架构寄存器更长的地址，允许更长的向量和更高效的处理器操作。

公开(公告)号：US20130054896A1

公开(公告)日：2013-02-28

申请号：US13591034

申请日：2012-08-21

Applicant: Osvaldo M. Colavin

Inventor： Osvaldo M. Colavin

IPC: G06F12/08

CPC classification number: G06F12/084 ,  G06F12/1458 ,  G06F2212/1028 ,  Y02D10/13

Abstract: A memory controller including a cache can be implemented in a system-on-chip. A cache allocation policy may be determined on the fly by the source of each memory request. The operators on the SoC allowed to allocate in the cache can be maintained under program control. Cache and system memory may be accessed simultaneously. This can result in improved performance and reduced power dissipation. Optionally, memory protection can be implemented, where the source of a memory request can be used to determine the legality of an access. This can simplifies software development when solving bugs involving non protected illegal memory accesses and can improves the system's robustness to the occurrence of errant processes.

Abstract translation: 包括缓存的存储器控​​制器可以在片上系统中实现。 缓存分配策略可以由每个存储器请求的来源随时确定。 允许在缓存中分配的SoC上的运营商可以在程序控制下进行维护。 可以同时访问缓存和系统内存。 这可以提高性能并降低功耗。 可选地，可以实现存储器保护，其中可以使用存储器请求的来源来确定访问的合法性。 这可以在解决涉及非保护的非法内存访问的错误时简化软件开发，并可以提高系统对发生错误进程的鲁棒性。

公开(公告)号：US07079160B2

公开(公告)日：2006-07-18

申请号：US10909817

申请日：2004-08-02

Applicant: Osvaldo M. Colavin

Inventor： Osvaldo M. Colavin

IPC: G09G5/00 ,  G06F12/00

CPC classification number: G09G5/346 ,  G09G5/34 ,  G09G2360/121

Abstract: A method and apparatus for buffering 2-dimensional graphical image data to be supplied to a scrolling display controller. A 2-dimensional, circularly addressed linear data buffer is used to store a portion of an entire image. The data buffer is larger than the amount of data displayed at one time. A user enters scrolling commands and the display scrolls around the data initially in the buffer. New data is loaded into the buffer as the displayed data approaches the edge of the buffered data.

Abstract translation: 一种用于缓冲要提供给滚动显示控制器的二维图形数据的方法和装置。 二维，循环寻址的线性数据缓冲器用于存储整个图像的一部分。 数据缓冲区大于同时显示的数据量。 用户输入滚动命令，显示屏最初在缓冲区中滚动数据。 随着显示的数据接近缓冲数据的边缘，新的数据被加载到缓冲区中。

公开(公告)号：US08935515B2

公开(公告)日：2015-01-13

申请号：US12544250

申请日：2009-08-20

Applicant: Osvaldo M. Colavin ,  Davide Rizzo ,  Vineet Soni ,  William L. Schubert, Jr.

Inventor： Osvaldo M. Colavin ,  Davide Rizzo ,  Vineet Soni ,  William L. Schubert, Jr.

IPC: G06F9/30 ,  G06F9/45 ,  G06F9/345 ,  G06F9/38

CPC classification number: G06F8/45 ,  G06F9/30036 ,  G06F9/30065 ,  G06F9/3013 ,  G06F9/30134 ,  G06F9/30189 ,  G06F9/345 ,  G06F9/381 ,  G06F9/3824 ,  G06F9/3836 ,  G06F9/384 ,  G06F9/3867

Abstract: A processor that can execute instructions in either scalar mode or vector mode. In scalar mode, instructions are executed once per fetch. In vector mode, instructions are executed multiple times per fetch. In vector mode, the processor recognizes scalar variables and vector variables. Scalar variables may be assigned a fixed memory location. Vector variables use different physical locations at different iterations of the same instruction. The processor includes circuitry to automatically index addresses of vector variables for each iteration of the same instruction. This circuitry partitions a register into a vector region and a scalar region. Accesses to the vector region are automatically indexed based on the number of iterations of the instruction that have been performed.

公开(公告)号：US06801219B2

公开(公告)日：2004-10-05

申请号：US09920026

申请日：2001-08-01

Applicant: Osvaldo M. Colavin

Inventor： Osvaldo M. Colavin

IPC: G09G500

CPC classification number: G09G5/346 ,  G09G2360/121

Abstract: A method and apparatus for buffering 2-dimensional graphical image data to be supplied to a scrolling display controller. A 2-dimensional, circularly addressed data buffer is used to store a portion of an entire image. The data buffer is larger than the amount of data displayed at one time. A user enters scrolling commands and the display scrolls around the data initially in the buffer. New data is loaded into the buffer as the displayed data approaches the edge of the buffered data.

Abstract translation: 一种用于缓冲要提供给滚动显示控制器的二维图形数据的方法和装置。 二维循环寻址的数据缓冲器用于存储整个图像的一部分。 数据缓冲区大于同时显示的数据量。 用户输入滚动命令，显示屏最初在缓冲区中滚动数据。 随着显示的数据接近缓冲数据的边缘，新的数据被加载到缓冲区中。

公开(公告)号：US07840761B2

公开(公告)日：2010-11-23

申请号：US11096475

申请日：2005-04-01

Applicant: Osvaldo M. Colavin ,  Davide Rizzo

Inventor： Osvaldo M. Colavin ,  Davide Rizzo

IPC: G06F9/28 ,  G06F12/06

CPC classification number: G06F9/383

Abstract: A processor executes one or more prefetch threads and one or more main computing threads. Each prefetch thread executes instructions ahead of a main computing thread to retrieve data for the main computing thread, such as data that the main computing thread may use in the immediate future. Data is retrieved for the prefetch thread and stored in a memory, such as data fetched from an external memory and stored in a buffer. A prefetch controller determines whether the memory is full. If the memory is full, a cache controller stalls at least one prefetch thread. The stall may continue until at least some of the data is transferred from the memory to a cache for use by at least one main computing thread. The stalled prefetch thread or threads are then reactivated.

Abstract translation: 处理器执行一个或多个预取线程和一个或多个主计算线程。 每个预取线程在主计算线程之前执行指令以检索主计算线程的数据，例如主计算线程在不久的将来可能使用的数据。 针对预取线程检索数据并存储在存储器中，例如从外部存储器读取并存储在缓冲器中的数据。 预取控制器确定存储器是否已满。 如果内存已满，缓存控制器将至少停止一个预取线程。 停顿可以继续，直到至少一些数据从存储器传送到高速缓存以供至少一个主计算线程使用。 然后重新激活停滞的预取线程或线程。

公开(公告)号：US07064783B2

公开(公告)日：2006-06-20

申请号：US10053222

申请日：2001-10-23

Applicant: Osvaldo M. Colavin ,  Emmanuel Lusinchi

Inventor： Osvaldo M. Colavin ,  Emmanuel Lusinchi

IPC: H04N5/76

CPC classification number: G06T3/403 ,  G06T3/4038 ,  H04N5/2624 ,  H04N5/772 ,  H04N5/781 ,  H04N5/907

Abstract: A method for storing a plurality of still images to form a panoramic image. The method comprising the steps of receiving a first image forming a part of a series of images to form a panoramic image and storing the first image in memory. When one or more subsequent images after the first image are received the steps of calculating one or more panoramic parameters between a current image and a previous image stored in memory and storing the current image with the one or more panoramic parameters in memory are performed.

公开(公告)号：US09270855B2

公开(公告)日：2016-02-23

申请号：US13430661

申请日：2012-03-26

Applicant: Mirko Guarnera ,  Alfio Castorina ,  Giuseppe Spampinato ,  Osvaldo M. Colavin ,  John Bloomfield ,  Armand Hekimian ,  Beátrice Varichon

Inventor： Mirko Guarnera ,  Alfio Castorina ,  Giuseppe Spampinato ,  Osvaldo M. Colavin ,  John Bloomfield ,  Armand Hekimian

IPC: G06F3/12 ,  H04N1/04 ,  H04N1/207 ,  H04N1/195

CPC classification number: H04N1/0461 ,  H04N1/195 ,  H04N1/207 ,  H04N2201/0414 ,  H04N2201/0416

Abstract: An embodiment of an integrated scanner apparatus, includes a support surface for objects to be scanned, a scanner unit to perform a scanning movement relative to the support surface to capture images of portions of objects to be scanned, and a printer unit carried by a carriage mobile with respect to said support surface, wherein said scanner unit is carried by said carriage carrying said printer unit to be imparted said scanning movement by said carriage.

Abstract translation: 集成扫描仪装置的实施例包括用于待扫描的对象的支撑表面，扫描器单元，用于执行相对于支撑表面的扫描运动，以捕获待扫描物体的部分的图像;以及打印机单元，其由托架 可移动地支撑所述支撑表面，其中所述扫描器单元由携带所述打印机单元的托架承载，以由所述托架赋予所述扫描运动。

公开(公告)号：US20090106537A1

公开(公告)日：2009-04-23

申请号：US12341250

申请日：2008-12-22

Applicant: Osvaldo M. Colavin

Inventor： Osvaldo M. Colavin

IPC: G06F9/30

CPC classification number: G06F9/325 ,  G06F9/30076 ,  G06F9/3013 ,  G06F9/30138 ,  G06F9/30189 ,  G06F9/3824 ,  G06F9/3826 ,  G06F9/3838 ,  G06F9/384 ,  G06F9/3853 ,  G06F9/3867 ,  G06F9/3887

Abstract: An improved superscalar processor. The processor includes multiple lanes, allowing multiple instructions in a bundle to be executed in parallel. In vector mode, the parallel lanes may be used to execute multiple instances of a bundle, representing multiple iterations of the bundle in a vector run. Scheduling logic determines whether, for each bundle, multiple instances can be executed in parallel. If multiple instances can be executed in parallel, coupling circuitry couples an instance of the bundle from one lane into one or more other lanes. In each lane, register addresses are renamed to ensure proper execution of the bundles in the vector run. Additionally, the processor may include a register bank separate from the architectural register file. Renaming logic can generate addresses to this separate register bank that are longer than used to address architectural registers, allowing longer vectors and more efficient processor operation.

Abstract translation: 改进的超标量处理器 处理器包括多个通道，允许并行执行捆绑中的多个指令。 在向量模式中，并行通道可用于执行捆绑的多个实例，表示向量运行中捆绑的多次迭代。 调度逻辑决定了对于每个bundle，是否可以并行执行多个实例。 如果并行执行多个实例，耦合电路将一个实体的捆绑从一个通道耦合到一个或多个其他通道。 在每个通道中，重命名寄存器地址以确保在向量运行中正确执行捆绑。 此外，处理器可以包括与架构寄存器文件分离的寄存器组。 重命名逻辑可以为这个单独的寄存器组生成比用于寻址架构寄存器更长的地址，允许更长的向量和更高效的处理器操作。