公开(公告)号：US20040026713A1

公开(公告)日：2004-02-12

申请号：US10441096

申请日：2003-05-20

Applicant: Hitachi, Ltd.

Inventor： Tomonori Tanoue ,  Kazuhiro Mochizuki ,  Hiroji Yamada

IPC: H01L031/0328 ,  H01L031/0336 ,  H01L031/072 ,  H01L031/109

CPC classification number: H01L29/66318 ,  H01L24/32 ,  H01L29/0657 ,  H01L29/0692 ,  H01L29/41708 ,  H01L29/7371 ,  H01L2924/1305 ,  H01L2924/15787 ,  H01L2924/00

Abstract: A semiconductor device with high structural reliability and low parasitic capacitance is provided. In one example, the semiconductor device has a surface. The semiconductor device comprises a semiconductor region, wherein an emitter region, a base region, and a collector region are laminated from a side near a substrate of the semiconductor region; an insulating protection layer disposed on the surface; and a wiring layer disposed on the surface, the insulating protection layer forming a via hole from the side of the substrate of the semiconductor region, the via hole being formed to allow the wiring layer to make a contact to an electrode of the emitter region from a side of the substrate where the emitter region, the base region, and the collector region are laminated and where the semiconductor region is isolated.

Abstract translation: 提供具有高结构可靠性和低寄生电容的半导体器件。 在一个示例中，半导体器件具有表面。 半导体器件包括半导体区域，其中从半导体区域的衬底附近的一侧层叠发射极区域，基极区域和集电极区域; 设置在所述表面上的绝缘保护层; 以及设置在所述表面上的布线层，所述绝缘保护层从所述半导体区域的所述基板的侧面形成通孔，所述通孔形成为允许所述布线层与所述发射极区域的电极接触 衬底的一侧，其中发射极区域，基极区域和集电极区域被层叠并且半导体区域被隔离。

公开(公告)号：US20040016918A1

公开(公告)日：2004-01-29

申请号：US10321867

申请日：2002-12-17

Inventor： Mohammad H. S. Amin ,  Alexandre Zagoskin ,  Geordie Rose ,  Jeremy P. Hilton

IPC: H01L029/06 ,  H01L031/0328

CPC classification number: H01L27/18 ,  B82Y10/00 ,  G01R33/0358 ,  G06N10/00 ,  Y10S977/933

Abstract: A system and method for controlling an information state of a superconducting qubit having a superconducting loop that includes a bulk loop portion, a mesoscopic island portion, and two Josephson junctions separating the bulk loop portion from the mesoscopic island portion is described. The method includes applying a bias across the mesoscopic island portion. In one embodiment, the method includes driving a bias current in the superconducting loop. In one embodiment, the method includes driving a bias current in the superconducting loop by coupling a magnetic flux into the superconducting loop. In one embodiment, the control system includes a tank circuit inductively coupled to the superconducting loop. In one embodiment, entanglement between qubits is provided by connections between qubits to be entangled.

Abstract translation: 描述了一种用于控制超导量子比特的信息状态的系统和方法，该超导量子位具有包括本体环路部分，介观岛部分以及将体环部分与介观岛部分离的两个约瑟夫逊结的超导回路。 该方法包括在介观岛部分上施加偏压。 在一个实施例中，该方法包括驱动超导环路中的偏置电流。 在一个实施例中，该方法包括通过将磁通量耦合到超导环路来驱动超导环路中的偏置电流。 在一个实施例中，控制系统包括电感耦合到超导回路的储能回路。 在一个实施例中，通过待纠缠的量子位之间的连接来提供量子位之间的纠缠。

公开(公告)号：US20040012037A1

公开(公告)日：2004-01-22

申请号：US10197607

申请日：2002-07-18

Applicant: MOTOROLA, INC.

Inventor： Suresh Venkatesan ,  Papu D. Maniar

IPC: H01L031/0328

CPC classification number: H01L21/76251 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02488 ,  H01L21/02532 ,  H01L21/02538 ,  H01L21/02546 ,  H01L21/8258 ,  H01L27/0605

Abstract: High quality gallium arsenide (GaAs) (38) is grown over a thin germanium layer (26) and co-exists with silicon (40) for hetero-integration of devices. A bonded germanium wafer of silicon (22), oxide (24), and germanium (26) is formed and capped (30). The cap (30) and germanium layer (26) are partially removed so as to expose a silicon region (32) and leave a stack (31) of oxide, germanium, and capping layer on the silicon. Selective silicon is grown over the exposed silicon region. Silicon devices (36) are made in the selectively grown region of silicon (34). The remaining capping layer (30) is etched away to expose the thin layer of germanium (26). GaAs (38) is grown on the thin germanium layer (26), and GaAs devices (29) are built which can interoperate with the silicon devices (36). Alternatively, a smaller portion of the remaining cap (30) can be removed and germanium or silicon-germanium can be selectively grown on the exposed germanium (214) in order to form germanium or silicon-germanium devices (216). The smaller remaining cap can subsequently be removed to access the germanium and form GaAs devices (222) thereby allowing, GaAs, germanium-based, and silicon devices to co-exist.

Abstract translation: 高质量的砷化镓（GaAs）（38）生长在薄锗层（26）上，与硅（40）共存，用于器件的异质整合。 形成硅（22），氧化物（24）和锗（26）的结合锗晶片并封盖（30）。 部分地去除盖（30）和锗层（26），以暴露硅区域（32）并在硅上留下氧化物，锗和覆盖层的堆叠（31）。 选择性硅生长在暴露的硅区域上。 在硅（34）的选择性生长区域中制造硅器件（36）。 将剩余的覆盖层（30）蚀刻掉以暴露锗（26）的薄层。 在薄锗层（26）上生长GaAs（38），并且构建可与硅器件（36）互操作的GaAs器件（29）。 或者，可以去除剩余盖（30）的较小部分，并且可以在暴露的锗（214）上选择性地生长锗或硅 - 锗，以便形成锗或硅 - 锗装置（216）。 随后可以移除较小的剩余盖以进入锗并形成GaAs器件（222），从而允许GaAs，锗基和硅器件共存。

公开(公告)号：US20040012036A1

公开(公告)日：2004-01-22

申请号：US10418291

申请日：2003-04-18

Inventor： Kenji Kotani ,  Hiroshi Yano

IPC: H01L031/0328

CPC classification number: H01L29/66318 ,  H01L29/0821 ,  H01L29/7371

Abstract: This invention provides a hetero-junction bipolar transistor (HBT) in which both a base resistance and a base-collector parasitic capacitance are decreased. The HBT has a collector (C) 18, a base (B) 20 and an emitter (E) 26. The collector comprises an outer collector region and an inner collector region, a thickness of the outer collector region is greater than that of the inner region. The base comprises an intrinsic region and an extrinsic region on the outer collector region, while the intrinsic base disposed on the inner collector region. The emitter is disposed on both the intrinsic base and the extrinsic base, and has a band gap energy greater than that of the base.

Abstract translation: 本发明提供了一种其中基极电阻和基极集电极寄生电容都降低的异质结双极晶体管（HBT）。 HBT具有集电体（C）18，基极（B）20和发射极（E）26。集电体包括外部集电极区域和内部集电极区域，外部集电极区域的厚度大于 内部区域。 基底包括外部集电极区域上的本征区域和非本征区域，而内部基极设置在内部集电区域上。 发射极设置在内部基极和外部基极两者上，并且具有大于基极的带隙能量的带隙能量。

公开(公告)号：US20040007716A1

公开(公告)日：2004-01-15

申请号：US10196634

申请日：2002-07-15

Inventor： Joe Trogolo ,  Tathagata Chatterlee ,  Lily Springer ,  Jeff Smith

IPC: H01L031/0328 ,  H01L031/0336 ,  H01L029/70 ,  H01L027/082

CPC classification number: H01L29/66272 ,  H01L21/8249 ,  H01L29/0804

Abstract: Disclosed are apparatus and methods for designing electrical contact for a bipolar emitter structure. The area of an emitter structure (106, 306, 400, 404) and the required current density throughput of an electrical contact structure (108, 308, 402, 406) are determined. A required electrical contact area is determined based on the required current density, and the electrical contact structure is then designed to minimize the required electrical contact area with respect to the emitter structure area.

Abstract translation: 公开了用于设计双极发射器结构的电接触的装置和方法。 确定发射极结构（106,306,404,404）的面积和电接触结构（108,308,402,406）所需的电流密度通过量。 基于所需的电流密度确定所需的电接触面积，并且然后设计电接触结构以将所需的电接触面积相对于发射器结构区域最小化。

公开(公告)号：US20030230788A1

公开(公告)日：2003-12-18

申请号：US10286754

申请日：2002-11-04

Applicant: Mitsubishi Denki Kabushiki Kaisha

Inventor： Hidenori Fujii

IPC: H01L031/0328 ,  H01L031/0336 ,  H01L027/082 ,  H01L027/102 ,  H01L029/70

CPC classification number: H01L29/66287 ,  H01L21/76202 ,  H01L29/0804 ,  H01L29/1004 ,  H01L29/41708 ,  H01L29/7322

Abstract: In an element formation region, a surface of an Nnull epitaxial layer is inclined upward from an end of a field oxide film to a sidewall of an opening. An external base diffusion layer formed on the surface of the Nnull epitaxial layer is inclined upward from a side of the field oxide film to the sidewall of the opening, and is exposed at the sidewall of the opening. A portion of the sidewall of the opening exposing the external base diffusion layer is tapered. A depth of a lower end of the external base diffusion layer on the sidewall of the opening is substantially equal to or smaller than that of a bottom of the opening. With this, decrease in breakdown voltage between an emitter and a base is suppressed, and decrease and variation of a current gain hFE is suppressed.

Abstract translation: 在元件形成区域中，N +外延层的表面从场氧化膜的端部向上倾斜到开口的侧壁。 形成在N +外延层的表面上的外部基极扩散层从场氧化膜的一侧向上倾斜到开口的侧壁，并且在开口的侧壁处露出。 露出外部基底扩散层的开口的侧壁的一部分是锥形的。 开口侧壁上的外部基底扩散层的下端的深度基本上等于或小于开口底部的深度。 由此，抑制了发射极与基极之间的击穿电压的降低，并且抑制了电流增益hFE的降低和变化。

公开(公告)号：US20030230766A1

公开(公告)日：2003-12-18

申请号：US10441678

申请日：2003-05-20

Inventor： Hitoshi Miyamoto

IPC: H01L031/0328

CPC classification number: H01L29/7802 ,  H01L21/823456 ,  H01L21/823487 ,  H01L29/0696 ,  H01L29/42372 ,  H02M3/335

Abstract: MOS transistor cells 1 and MOS transistor cells 2 having different gate threshold voltages are formed on a chip 8. The MOS transistor cells 1, 2 having the different gate threshold voltages are connected in parallel.

Abstract translation: 在芯片8上形成具有不同栅极阈值电压的MOS晶体管单元1和MOS晶体管单元2.具有不同栅极阈值电压的MOS晶体管单元1,2并联连接。

公开(公告)号：US20030222278A1

公开(公告)日：2003-12-04

申请号：US10449941

申请日：2003-05-30

Applicant: NATIONAL CHENG KUNG UNIVERSITY

Inventor： Wen-Chau Liu ,  Shiou-Ying Cheng

IPC: H01L031/0328

CPC classification number: H01L29/66318 ,  H01L29/7371

Abstract: A bipolar heterojunction transistor (HBT) includes a collector layer, a base layer formed on the collector layer, a first transition layer formed on the base layer, an emitter layer formed on the first transition layer, a second transition layer formed on the emitter layer, and an emitter cap layer formed on the second transition layer. Each of the first and second transition layers is formed of a composition that contains an element, the mole fraction of which is graded in such a manner that the conduction band of the HBT is continuous through the base layer, the first and second transition layers, the emitter layer and the emitter cap layer.

Abstract translation: 双极异质结晶体管（HBT）包括集电极层，形成在集电极层上的基极层，形成在基极层上的第一过渡层，形成在第一过渡层上的发射极层，形成在发射极层上的第二过渡层 以及形成在第二过渡层上的发射极帽层。 第一和第二过渡层中的每一个由包含元素的组合物形成，该元素的摩尔分数以使得HBT的导带连续穿过基底层，第一和第二过渡层的方式分级， 发射极层和发射极盖层。

公开(公告)号：US20030222277A1

公开(公告)日：2003-12-04

申请号：US10279055

申请日：2002-10-24

Applicant: Mitsubishi Denki Kabushiki Kaisha

Inventor： Hidenori Fujii

IPC: H01L031/0328 ,  H01L031/0336 ,  H01L031/072 ,  H01L031/109

CPC classification number: H01L29/66272 ,  H01L29/1004 ,  H01L29/34

Abstract: Impurity of a conductivity type for formation of an intrinsic base diffusion layer and impurity of the opposite conductivity type are implanted into a semiconductor substrate. An exposed surface of the semiconductor substrate is irradiated with plasma, so that many crystal defects are produced therein. Next, a polysilicon film is formed under the condition causing the grain size to increase. In a portion of the polysilicon film located near the exposed surface of the semiconductor substrate, the grain size becomes relatively small influenced by the crystal defects in the substrate surface. In a portion of the polysilicon film located on the silicon oxide film, the grain size becomes relatively large uninfluenced by the crystal defects. Thus, degradation of electric characteristics is suppressed, and variation in resistance value of the resistance element is alleviated.

Abstract translation: 用于形成本征基极扩散层的导电类型和相反导电类型的杂质的杂质被注入到半导体衬底中。 用等离子体照射半导体衬底的暴露表面，从而在其中产生许多晶体缺陷。 接下来，在使晶粒尺寸增大的条件下形成多晶硅膜。 在位于半导体衬底的暴露表面附近的多晶硅膜的一部分中，由于衬底表面中的晶体缺陷，晶粒尺寸变得相对较小。 在位于氧化硅膜上的多晶硅膜的一部分中，晶粒尺寸变得相对较大，不受晶体缺陷的影响。 因此，电特性的劣化被抑制，并且电阻元件的电阻值的变化得到缓解。

公开(公告)号：US20030218190A1

公开(公告)日：2003-11-27

申请号：US10373670

申请日：2003-02-24

Applicant: SEIKO EPSON CORPORATION

Inventor： Nobuaki Hashimoto

IPC: H01L031/0328

CPC classification number: H05K3/361 ,  H01L2224/73204 ,  H05K1/117 ,  H05K3/28 ,  H05K3/305 ,  H05K3/4007 ,  H05K2201/0367 ,  H05K2201/09709 ,  H05K2201/10977 ,  H05K2203/0369

Abstract: A plurality of lands are arranged in rows. The lands in adjacent rows are disposed in a staggered arrangement. A first interconnecting line is pulled out from each of the lands. Each of the lands is wider than the first interconnecting line in the row direction. A plurality of electrical connection sections are arranged in rows. The electrical connection sections in adjacent rows are disposed in a staggered arrangement. The lands are electrically connected with the electrical connection sections so as to overlap. Each of the electrical connection sections is a part of a second interconnecting line, and an insulating layer is formed between the second interconnecting lineing pattern other than the electrical connection sections and the first interconnecting lineing pattern.

Abstract translation: 多个平台排成行。 相邻行中的平台以交错排列布置。 从每个焊盘拉出第一互连线。 每个平台比行方向上的第一互连线宽。 多个电连接部分排列成行。 相邻行中的电连接部分以交错布置设置。 焊盘与电连接部分电连接以便重叠。 每个电连接部分是第二互连线的一部分，并且绝缘层形成在第二互连线图案之外，而不是电连接部分和第一互连线条图案。