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    Offset-aligned three-dimensional integrated circuit
    391.
    发明授权
    Offset-aligned three-dimensional integrated circuit 有权

    公开(公告)号：US11437359B2

    公开(公告)日：2022-09-06

    申请号：US16799243

    申请日：2020-02-24

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Brett P. Wilkerson ,  Milind S. Bhagavat ,  Rahul Agarwal ,  Dmitri Yudanov

    IPC: H01L25/18 ,  H01L23/367 ,  H01L23/00 ,  H01L25/00 ,  H01L23/48

    Abstract: A method for manufacturing a three-dimensional integrated circuit includes attaching a first side of a first die to a first carrier wafer. The method includes preparing a second side of the first die to generate a prepared second side of the first die. The method includes attaching the prepared second side of the first die to a second carrier wafer. The method includes removing the first carrier wafer from the first side of the first die to form a transitional three-dimensional integrated circuit. The method includes attaching a third carrier wafer to a first side of the transitional three-dimensional integrated circuit. The method includes attaching a first side of the second die to a second side of the transitional three-dimensional integrated circuit.

    Proactive management of inter-GPU network links
    392.
    发明授权
    Proactive management of inter-GPU network links 有权

    公开(公告)号：US11436060B2

    公开(公告)日：2022-09-06

    申请号：US16552065

    申请日：2019-08-27

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Karthik Rao ,  Abhinav Vishnu

    IPC: G06F9/46 ,  G06F9/50 ,  G06N3/08 ,  G06F9/54 ,  G06F9/38

    Abstract: Systems, apparatuses, and methods for proactively managing inter-processor network links are disclosed. A computing system includes at least a control unit and a plurality of processing units. Each processing unit of the plurality of processing units includes a compute module and a configurable link interface. The control unit dynamically adjusts a clock frequency and a link width of the configurable link interface of each processing unit based on a data transfer size and layer computation time of a plurality of layers of a neural network so as to reduce execution time of each layer. By adjusting the clock frequency and the link width of the link interface on a per-layer basis, the overlapping of communication and computation phases is closely matched, allowing layers to complete more quickly.

    Techniques for improving operand caching
    393.
    发明授权
    Techniques for improving operand caching 有权

    公开(公告)号：US11436016B2

    公开(公告)日：2022-09-06

    申请号：US16703833

    申请日：2019-12-04

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Anthony T. Gutierrez ,  Bradford M. Beckmann ,  Marcus Nathaniel Chow

    IPC: G06F9/30 ,  G06F9/38

    Abstract: A technique for determining whether a register value should be written to an operand cache or whether the register value should remain in and not be evicted from the operand cache is provided. The technique includes executing an instruction that accesses an operand that comprises the register value, performing one or both of a lookahead technique and a prediction technique to determine whether the register value should be written to an operand cache or whether the register value should remain in and not be evicted from the operand cache, and based on the determining, updating the operand cache.

    Scheduling memory requests for a ganged memory device
    396.
    发明授权
    Scheduling memory requests for a ganged memory device 有权

    公开(公告)号：US11422707B2

    公开(公告)日：2022-08-23

    申请号：US15851479

    申请日：2017-12-21

    Applicant: Advanced Micro Devices, Inc.

    Inventor： James Raymond Magro

    IPC: G06F13/16 ,  G06F9/50 ,  G06F3/06 ,  G06F12/10

    Abstract: Systems, apparatuses, and methods for performing efficient memory accesses for a computing system are disclosed. A computing system includes one or more clients for processing applications. A memory controller transfers traffic between the memory controller and two channels, each connected to a memory device. A client sends a 64-byte memory request with an indication specifying that there are two 32-byte requests targeting non-contiguous data within a same page. The memory controller generates two addresses, and sends a single command and the two addresses to two channels to simultaneously access non-contiguous data in a same page.

    Selectively performing ahead branch prediction based on types of branch instructions
    397.
    发明授权
    Selectively performing ahead branch prediction based on types of branch instructions 有权

    公开(公告)号：US11416256B2

    公开(公告)日：2022-08-16

    申请号：US16945275

    申请日：2020-07-31

    Applicant: ADVANCED MICRO DEVICES, INC.

    Inventor： Marius Evers ,  Aparna Thyagarajan ,  Ashok T. Venkatachar

    IPC: G06F15/00 ,  G06F7/38 ,  G06F9/00 ,  G06F9/44 ,  G06F9/38 ,  G06F9/355 ,  G06F9/35

    Abstract: A set of entries in a branch prediction structure for a set of second blocks are accessed based on a first address of a first block. The set of second blocks correspond to outcomes of one or more first branch instructions in the first block. Speculative prediction of outcomes of second branch instructions in the second blocks is initiated based on the entries in the branch prediction structure. State associated with the speculative prediction is selectively flushed based on types of the branch instructions. In some cases, the branch predictor can be accessed using an address of a previous block or a current block. State associated with the speculative prediction is selectively flushed from the ahead branch prediction, and prediction of outcomes of branch instructions in one of the second blocks is selectively initiated using non-ahead accessing, based on the types of the one or more branch instructions.

    INSET POWER POST AND STRAP ARCHITECTURE WITH REDUCED VOLTAGE DROOP
    400.
    发明申请
    INSET POWER POST AND STRAP ARCHITECTURE WITH REDUCED VOLTAGE DROOP 有权

    公开(公告)号：US20220208678A1

    公开(公告)日：2022-06-30

    申请号：US17135122

    申请日：2020-12-28

    Applicant: ADVANCED MICRO DEVICES, INC.

    Inventor： Richard SCHULTZ

    IPC: H01L23/528 ,  H01L23/522 ,  H01L27/092 ,  H01L29/45 ,  H01L21/285 ,  H01L21/8238

    Abstract: A cell layout implemented in an integrated circuit (IC) includes a first plurality of independent power posts in a first metal layer. Each independent power post of the plurality of independent power posts provides a power connection to one device of a plurality of devices within the cell layout. A source or drain of each device of the plurality of devices is connected to one independent power post of the plurality of independent power posts. The IC further includes a plurality of independent power straps in a second metal layer that is different from the first metal layer. Each independent power strap of the plurality of independent power straps spans across and connects to multiple independent power posts of the first plurality of independent power posts.

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