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    Memory Systems and Methods for Improved Power Management
    401.
    发明申请
    Memory Systems and Methods for Improved Power Management 审中-公开

    公开(公告)号：US20200152258A1

    公开(公告)日：2020-05-14

    申请号：US16693071

    申请日：2019-11-22

    Applicant: Rambus Inc.

    Inventor： Frederick A. Ware ,  James E. Harris

    IPC: G11C11/4093 ,  G11C7/22 ,  G11C8/12 ,  G11C5/06 ,  G11C5/04

    Abstract: A memory module with multiple memory devices includes a buffer system that manages communication between a memory controller and the memory devices. Each memory device supports an access mode and a low-power mode, the latter used to save power for devices that are not immediately needed. The module provides granular power management using a chip-select decoder that decodes chip-select signals from the memory controller into power-state signals that determine which of the memory devices are in which of the modes. Devices can thus be brought out of the low-power mode in relatively small numbers, as needed, to limit power consumption.

    Memory system with threaded transaction support
    404.
    发明授权
    Memory system with threaded transaction support 有权

    公开(公告)号：US10592120B2

    公开(公告)日：2020-03-17

    申请号：US15529970

    申请日：2015-12-18

    Applicant: Rambus Inc.

    Inventor： Frederick A. Ware ,  Ely Tsern

    IPC: G06F3/06 ,  G11C5/04 ,  G11C7/10 ,  G06F12/06

    Abstract: Memory modules, systems, memory controllers and associated methods are disclosed. In one embodiment, a memory module includes a module substrate having first and second memory devices. Buffer circuitry disposed on the substrate couples to the first and second memory devices via respective first and second secondary interfaces. The buffer circuitry includes a primary signaling interface for coupling to a group of signaling links associated with a memory controller. The primary signaling interface operates at a primary signaling rate and the first and second secondary data interfaces operate at a secondary signaling rate. During a first mode of operation, the primary interface signaling rate is at least twice the secondary signaling rate. A first time interval associated with a transfer of first column data via the first secondary interface temporally overlaps a second time interval involving second column data transferred via the second secondary interface.

    INTERFACE FOR MEMORY READOUT FROM A MEMORY COMPONENT IN THE EVENT OF FAULT
    405.
    发明申请
    INTERFACE FOR MEMORY READOUT FROM A MEMORY COMPONENT IN THE EVENT OF FAULT 审中-公开

    公开(公告)号：US20200050562A1

    公开(公告)日：2020-02-13

    申请号：US16548714

    申请日：2019-08-22

    Applicant: Rambus Inc.

    Inventor： Frederick A. Ware ,  Kenneth L. Wright

    IPC: G06F13/16 ,  G06F11/07 ,  G06F13/40

    Abstract: Memory controllers, devices, modules, systems and associated methods are disclosed. In one embodiment, an integrated circuit (IC) memory component is disclosed that includes a memory core, a primary interface, and a secondary interface. The primary interface includes data input/output (I/O) circuitry and control/address (C/A) input circuitry, and accesses the memory core during a normal mode of operation. The secondary interface accesses the memory core during a fault mode of operation.

    Periodic calibration for communication channels by drift tracking
    406.
    发明授权
    Periodic calibration for communication channels by drift tracking 有权

    公开(公告)号：US10523344B2

    公开(公告)日：2019-12-31

    申请号：US16393817

    申请日：2019-04-24

    Applicant: Rambus Inc.

    Inventor： Craig E. Hampel ,  Frederick A. Ware ,  Richard E. Perego

    IPC: H04L7/00 ,  H04L7/04 ,  H04B17/11 ,  H04B17/21 ,  H04L27/00 ,  H04L7/10 ,  H04B17/00

    Abstract: A method and system that provides for execution of a first calibration sequence, such as upon initialization of a system, to establish an operation value, which utilizes an algorithm intended to be exhaustive, and executing a second calibration sequence from time to time, to measure drift in the parameter, and to update the operation value in response to the measured drift. The second calibration sequence utilizes less resources of the communication channel than does the first calibration sequence. In one embodiment, the first calibration sequence for measurement and convergence on the operation value utilizes long calibration patterns, such as codes that are greater than 30 bytes, or pseudorandom bit sequences having lengths of 2N−1 bits, where N is equal to or greater than 7, while the second calibration sequence utilizes short calibration patterns, such as fixed codes less than 16 bytes, and for example as short as 2 bytes long.

    Strobe Acquisition and Tracking
    407.
    发明申请
    Strobe Acquisition and Tracking 审中-公开

    公开(公告)号：US20190392875A1

    公开(公告)日：2019-12-26

    申请号：US16459330

    申请日：2019-07-01

    Applicant: Rambus Inc.

    Inventor： Bret Stott ,  Frederick A. Ware ,  Ian P. Shaeffer ,  Yuanlong Wang

    IPC: G11C7/22 ,  G11C7/02 ,  G06F13/16

    Abstract: A memory controller includes an interface to receive a data strobe signal and corresponding read data. The data strobe signal and the read data correspond to a read command issued by the memory controller, and the read data is received in accordance with the data strobe signal and an enable signal. A circuit in the memory controller is to dynamically adjust a timing offset between the enable signal and the data strobe signal, and control logic is to issue a supplemental read command in accordance with a determination that a time interval since a last read command issued by the memory controller exceeds a predetermined value.

    Domain-distributed cryogenic signaling amplifier
    409.
    发明授权
    Domain-distributed cryogenic signaling amplifier 有权

    公开(公告)号：US10511276B1

    公开(公告)日：2019-12-17

    申请号：US16043754

    申请日：2018-07-24

    Applicant: Rambus Inc.

    Inventor： Frederick A. Ware ,  Carl W. Werner ,  John Eric Linstadt

    IPC: H03F1/02 ,  H03F1/30 ,  H03F3/16 ,  H03F19/00 ,  G06N10/00

    Abstract: A signal amplifier is distributed between first and second IC devices and includes a low-power input stage disposed within the first IC device, a bias-current source disposed within the second IC device and an output stage disposed within the second IC device. The output stage includes a resistance disposed within the second IC device and having a first terminal coupled to a drain terminal of a transistor within the input stage via a first signaling line that extends between the first and second IC devices.

    Protocol for refresh between a memory controller and a memory
    410.
    发明授权
    Protocol for refresh between a memory controller and a memory 有权

    公开(公告)号：US10510395B2

    公开(公告)日：2019-12-17

    申请号：US16032575

    申请日：2018-07-11

    Applicant: Rambus Inc.

    Inventor： Frederick A. Ware ,  Brent Haukness

    IPC: G06F12/00 ,  G11C11/406 ,  G06F13/16

    Abstract: The present embodiments provide a system that supports self-refreshing operations in a memory device. During operation, the system transitions the memory device from an auto-refresh state, wherein a memory controller controls refreshing operations for the memory device, to a self-refresh state, wherein the memory device controls the refreshing operations. While the memory device is in the self-refresh state, the system sends progress information for the refreshing operations from the memory device to the memory controller. Next, upon returning from the self-refresh state to the auto-refresh state, the system uses the progress information received from the memory device to control the sequencing of subsequent operations by the memory controller.

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