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公开(公告)号：US11728623B2
公开(公告)日：2023-08-15
申请号：US17247401
申请日：2020-12-10
Applicant: Mellanox Technologies, Ltd.
Inventor： Yuri Berk , Vladimir Iakovlev , Tamir Sharkaz , Elad Mentovich
CPC classification number: H01S5/18347 , H01S5/18311 , H01S5/18377 , H01S5/2275 , H01S5/3095 , H01S5/3401 , H01S5/423
Abstract: A vertical-cavity surface-emitting laser (VCSEL) is provided that includes a mesa structure disposed on a substrate. The mesa structure defines an emission axis of the VCSEL. The mesa structure includes a first reflector, a second reflector, and a cascaded active region structure disposed between the first reflector and the second reflector. The cascaded active region structure includes a plurality of cascaded active region layers disposed along the emission axis, where each of the cascade active region layers includes an active region having multi-quantum well and/or dots layers (MQLs), a tunnel junction aligned with the emission axis, and an oxide confinement layer. The oxide confinement layer is disposed between the tunnel junction and MQLs, and has an electrical current aperture defined therein. The mesa structure defines an optical window through which the VCSEL is configured to emit light.
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公开(公告)号：US11726279B2
公开(公告)日：2023-08-15
申请号：US17717623
申请日：2022-04-11
Applicant: Mellanox Technologies, Ltd.
Inventor： Ilya Margolin , Rony Setter , Andrey Ger , Yaniv Kazav , Tarek Hathoot
CPC classification number: G02B6/4261 , G02B6/4284 , H04B10/40
Abstract: Apparatuses, systems, and methods are described that provide improved networking communication systems and associated adapters. An example networking communication adapter includes an adapter housing defining a first end and a second end opposite the first end. The first end is configured to engage an Octal Small Form Factor Pluggable (OSFP) connector, and the second end is configured to receive a Quad Small Form Factor Pluggable Double Density (QSFP-DD) transceiver therein. The networking communication adapter further includes an inner connector positioned within the adapter housing. In an operational configuration in which the first end engages the OSFP connector and the second end receives the QSFP-DD transceiver, the inner connector operably connects the QSFP-DD transceiver with the OSFP connector such that signals may pass therebetween.
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公开(公告)号：US20230239068A1
公开(公告)日：2023-07-27
申请号：US17665600
申请日：2022-02-07
Applicant: MELLANOX TECHNOLOGIES, LTD.
Inventor： Dotan David Levi , Ioannis (Giannis) Patronas , Wojciech Wasko , Paraskevas Bakopoulos , Dimitrios Syrivelis , Elad Mentovich
CPC classification number: H04J14/08 , H04J14/0212 , H04J14/0267
Abstract: A network adapter includes a host interface and a scheduler. The host interface is configured to receive, from one or more hosts, packets for transmission to respective destinations over a network. The scheduler is configured to synchronize to a time-division schedule that is employed in the network, the time-division schedule specifying (i) multiple time-slots and (ii) multiple respective groups of the destinations that are reachable during the time-slots, and, based on the time-division schedule, to schedule transmission times of the packets to the network on time-slots during which the respective destinations of the packets are reachable.
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公开(公告)号：US20230238358A1
公开(公告)日：2023-07-27
申请号：US17584450
申请日：2022-01-26
Applicant: Mellanox Technologies, Ltd.
Inventor： Ido Bourstein
IPC: H01L25/065 , H01L23/00 , G03F1/20
CPC classification number: H01L25/0657 , H01L24/08 , H01L24/06 , H01L24/80 , G03F1/20 , H01L2224/08145 , H01L2224/06177 , H01L2224/80895
Abstract: An electronic device includes a first integrated circuit (IC) die and a second IC die. The first IC die includes a first set of contact pads arranged in a first geometrical pattern on a first surface of the first IC die, the second IC die includes a second set of the contact pads that are arranged, on a second surface of the second IC die, in a second geometrical pattern that is a mirror image of the first geometrical pattern. The second surface of the second IC die is facing the first surface of the first IC die, and the contact pads of the first and second sets are aligned with one another and mounted on one another.
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公开(公告)号：US20230236624A1
公开(公告)日：2023-07-27
申请号：US17582058
申请日：2022-01-24
Applicant: MELLANOX TECHNOLOGIES, LTD.
Inventor： Dotan David Levi , Wojciech Wasko , Eitan Zahavi , Natan Manevich , Bar Shapira
CPC classification number: G06F1/14 , H04J3/0697 , H04J3/0682 , H04J3/0661 , H04J3/0679 , G06F1/12
Abstract: In one embodiment, a device includes a hardware clock to maintain a clock value, a hardware counter to maintain an estimation of a dynamic error bound of the clock value, and a clock controller to intermittently discipline the hardware clock responsively to a remote clock, advance the hardware counter at a rate responsively to a clock drift, and adjust the hardware counter responsively to the hardware clock being disciplined.
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Patent Agency Ranking
公开(公告)号：US20230213835A1
公开(公告)日：2023-07-06
申请号：US17694159
申请日：2022-03-14
Applicant: Mellanox Technologies, Ltd.
Inventor： Nikos Argyris , Paraskevas Bakopoulos , Dimitrios Kalavrouziotis , Elad Mentovich
CPC classification number: G02F1/212 , H04B10/505 , G02F1/225
Abstract: Embodiments are disclosed for providing a serializer and/or a deserializer with redundancy using optical modulators. An example system includes an MZM structure that comprises a first waveguide interferometer arm structure and a second waveguide interferometer arm structure. The first waveguide interferometer arm structure comprises a first segmented electrode associated with at least a first electrode and a second electrode. The second waveguide interferometer arm structure comprises a second segmented electrode associated with at least a third electrode and a fourth electrode. The MZM structure is configured to convert an optical input signal into an optical output signal through application of a digital data signal to the first electrode and the third electrode, and application of a redundant digital data signal to the second electrode and the fourth electrode.
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公开(公告)号：US20230187858A1
公开(公告)日：2023-06-15
申请号：US17548688
申请日：2021-12-13
Applicant: Mellanox Technologies Ltd.
Inventor： Tamir LEDERMAN , Aziz MAZBAR , Tomer KLEIN , Alexander SHUSTERMAN , Andrey GER
CPC classification number: H01R12/7052 , H05K1/181 , H05K2201/09063 , H05K2201/10189
Abstract: A device may include a frame, a first leg extending from the frame, and a second leg extending from the frame, wherein each of the first leg and the second leg is curved in a respective direction, the respective directions being different.
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公开(公告)号：US11664983B2
公开(公告)日：2023-05-30
申请号：US17122140
申请日：2020-12-15
Applicant: Mellanox Technologies, Ltd.
Inventor： Elad Mentovich , Itshak Kalifa , Ioannis (Giannis) Patronas , Paraskevas Bakopoulos , Eyal Waldman
CPC classification number: H04L9/0858 , H04B10/70
Abstract: Embodiments are disclosed for a quantum key distribution enabled intra-datacenter network. An example system includes a first vertical cavity surface emitting laser (VCSEL), a second VCSEL and a network interface controller. The first VCSEL is configured to emit a first optical signal associated with data. The second VCSEL is configured to emit a second optical signal associated with quantum key distribution (QKD). Furthermore, the network interface controller is configured to manage transmission of the first optical signal associated with the first VCSEL and the second optical signal associated with the second VCSEL via an optical communication channel coupled to a network interface module.
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公开(公告)号：US20230163869A1
公开(公告)日：2023-05-25
申请号：US17534776
申请日：2021-11-24
Applicant: MELLANOX TECHNOLOGIES, LTD.
Inventor： Bar Shapira , Ariel Almog , Dotan David Levi , Natan Manevich , Thomas Kernen , Liron Mula
IPC: H04J3/06
CPC classification number: H04J3/0638
Abstract: A system for maintaining a Precision Time Protocol (PTP) hardware clock, the system being operative in conjunction with a network device which is external to the system, the system comprising a controller to receive information characterizing a network peer oscillator frequency, wherein the information was extracted from an RX symbol rate, and to adjust the PTP Hardware Clock's frequency responsive to the information characterizing the network peer oscillator frequency.
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公开(公告)号：US20230139481A1
公开(公告)日：2023-05-04
申请号：US17955583
申请日：2022-09-29
Applicant: MELLANOX TECHNOLOGIES, LTD.
Inventor： Roni Bar Yanai , Jiawei Wang , Yossef Efraim , Chen Rozenbaum
IPC: H04L47/2483 , H04L45/748
Abstract: A method includes providing a library of hardware-agnostic packet-processing functions. A functional hardware-agnostic specification of a packet-processing pipeline, for use in a network device, is received from a user. The specification is defined in terms of one or more of the packet-processing functions draws from the library. A hardware-specific design of the packet-processing pipeline, which is suited to given hardware, is derived from the specification.
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