公开(公告)号：US11171644B2

公开(公告)日：2021-11-09

申请号：US17207382

申请日：2021-03-19

Applicant: STMicroelectronics S.r.l. ,  STMicroelectronics (Rousset) SAS

Inventor： Antonino Conte ,  Francesco Tomaiuolo ,  Francesco La Rosa

IPC: H03K17/14 ,  H03K17/22

Abstract: An embodiment power-on-reset circuit, having a power supply input to receive a power supply voltage, generates a reset signal with a value switching upon the power supply voltage crossing a POR detection level. The power-on-reset circuit has: a PTAT stage having a left branch and a right branch and generating a current equilibrium condition between the currents circulating in the left and right branches upon the power supply voltage reaching the POR detection level; and an output stage coupled to the PTAT stage and generating the reset signal, with the value switching at the occurrence of the current equilibrium condition for the PTAT stage. The power-on-reset circuit further comprises a detection-level generation stage, coupled to the PTAT stage as a central branch thereof to define the value of the POR detection level.

公开(公告)号：US20210335994A1

公开(公告)日：2021-10-28

申请号：US17370397

申请日：2021-07-08

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Pascal FORNARA

IPC: H01L29/04 ,  H01L29/66 ,  H01L29/861 ,  H01L29/868

Abstract: A diode is formed by a polycrystalline silicon bar which includes a first doped region with a first conductivity type, a second doped region with a second conductivity type and an intrinsic region between the first and second doped regions. A conductive layer extends parallel to the polycrystalline silicon bar and separated from the polycrystalline silicon bar by a dielectric layer. The conductive layer is configured to be biased by a bias voltage.

公开(公告)号：US20210319191A1

公开(公告)日：2021-10-14

申请号：US17357182

申请日：2021-06-24

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Nicolas Cordier ,  Anthony Tornambe

IPC: G06K7/10

Abstract: An operation of calibrating the object using a reference reader is performed, the calibration operation including an operation of placing the reference reader at various distances away from the object that correspond to various values of a parameter within the object that is representative of the intensity of the signal received by the object, and, for each distance, an operation of determining an internal phase-shift compensation in the object with respect to a nominal internal phase shift, making it possible to obtain a load modulation amplitude that is higher, in terms of absolute value, than a threshold, and an operation of storing a lookup table of the various values of the parameter and the corresponding internal phase-shift compensations.

公开(公告)号：US11133798B2

公开(公告)日：2021-09-28

申请号：US16856448

申请日：2020-04-23

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Nicolas Froidevaux ,  Laurent Lopez

IPC: H03K17/687 ,  H03K17/30

Abstract: A device includes a first connection pin, a second connection pin, a third connection pin, and a fourth connection pin. The second connection pin is configured to be connected to a supply voltage. The fourth connection pin is configured to be coupled to a reference voltage. The device further includes a first transistor including: a first gate and a first source/drain coupled to the first connection pin; a second transistor including a second gate and a second source/drain connected to the first transistor; and a third transistor including a third gate, a third source/drain connected to the second transistor, and a fourth source/drain connected to the fourth connection pin. The third transistor is configured to be controlled by a digital signal using the third connection pin. Both the first gate and the second gate are directly connected to the second connection pin.

公开(公告)号：US20210297074A1

公开(公告)日：2021-09-23

申请号：US17207382

申请日：2021-03-19

Applicant: STMicroelectronics S.r.I. ,  STMicroelectronics (Rousset) SAS

Inventor： Antonino Conte ,  Francesco Tomaiuolo ,  Francesco La Rosa

IPC: H03K17/22 ,  H03K17/14

Abstract: An embodiment power-on-reset circuit, having a power supply input to receive a power supply voltage, generates a reset signal with a value switching upon the power supply voltage crossing a POR detection level. The power-on-reset circuit has: a PTAT stage having a left branch and a right branch and generating a current equilibrium condition between the currents circulating in the left and right branches upon the power supply voltage reaching the POR detection level; and an output stage coupled to the PTAT stage and generating the reset signal, with the value switching at the occurrence of the current equilibrium condition for the PTAT stage. The power-on-reset circuit further comprises a detection-level generation stage, coupled to the PTAT stage as a central branch thereof to define the value of the POR detection level.

公开(公告)号：US20210286902A1

公开(公告)日：2021-09-16

申请号：US17199279

申请日：2021-03-11

Applicant: STMICROELECTRONICS (ROUSSET) SAS

Inventor： Yanis LINGE ,  Simon LANDRY

IPC: G06F21/72

Abstract: The present disclosure relates to a method of fault detection in an application, by an electronic circuit, of a first function to a message, including the steps of generating, from the message, a non-zero even number N of different first sets, each including P shares; applying, to the P shares of each first set, one or a plurality of second functions delivering, for each first set, a second set including Q images; and cumulating all the images, starting with at most Q-1 images selected from among the Q images of a same second set.

公开(公告)号：US11120878B2

公开(公告)日：2021-09-14

申请号：US16857937

申请日：2020-04-24

Applicant: STMicroelectronics (Rousset) SAS

Inventor： François Tailliet ,  Marc Battista

IPC: G11C16/12 ,  G11C16/04 ,  G11C16/08 ,  G11C16/24 ,  G11C16/30

Abstract: A method for programming a non-volatile memory (NVM) and an integrated circuit is disclosed. In an embodiment an integrated circuit includes a memory plane organized into rows and columns of memory words, each memory word comprising memory cells and each memory cell including a state transistor having a control gate and a floating gate and write circuitry configured to program a selected memory word during a programming phase by applying a first nonzero positive voltage to control gates of the state transistors of the memory cells that do not belong to the selected memory word.

公开(公告)号：US11115038B2

公开(公告)日：2021-09-07

申请号：US16923335

申请日：2020-07-08

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Bruno Gailhard ,  Laurent Truphemus ,  Christophe Eva

IPC: H03L7/10 ,  H03L7/089 ,  H03L7/099

Abstract: The operation of the phase-locked loop includes a startup phase where a reference signal having a duty cycle of 50% is applied to a phase comparator of the loop. A first divider of an output signal of the voltage-controlled oscillator of the loop is reset at each first type signal edge of the reference signal. The phase comparator receives the reference signal and a feedback signal from the first divider and generates a control pulse at each second type signal edge of the reference signal that causes a control voltage of the oscillator to increase.

公开(公告)号：US11114502B2

公开(公告)日：2021-09-07

申请号：US16566794

申请日：2019-09-10

Applicant: STMICROELECTRONICS (ROUSSET) SAS

Inventor： Philippe Boivin

IPC: H01L27/24 ,  H01L45/00

Abstract: The disclosure concerns a resistive memory cell, including a stack of a selector, of a resistive element, and of a layer of phase-change material, the selector having no physical contact with the phase-change material. In one embodiment, the selector is an ovonic threshold switch formed on a conductive track of a metallization level.

公开(公告)号：US11113384B2

公开(公告)日：2021-09-07

申请号：US15847827

申请日：2017-12-19

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Pierre Guillemin ,  William Orlando

IPC: G06F21/52 ,  G06F9/00

Abstract: A hardware monitor circuit includes an electronic control circuit coupled to a processing unit. The electronic control circuit generates multi-bit protection codes and directs operations of the hardware monitor circuit. A bus interface is coupled to an address bus of the processing unit, and the bus interface passes signals associated with a stack structure of the processing unit. The stack structure is arranged to store the multi-bit protection codes in an internal memory coupled to the processing unit. Comparators in the hardware monitor circuit are arranged to accept values from the internal memory and gating logic coupled to the comparators is arranged to generate an error signal when it detects that an address on the address bus read via the bus interface is equal to an address stored in the internal memory. Upon generating the error signal, the processing unit is placed in a secure mode.