中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

613 records (took 0.034 seconds)

    Non-volatile Memory Device With Stored Index Information
    413.
    发明申请
    Non-volatile Memory Device With Stored Index Information 有权

    公开(公告)号：US20210082517A1

    公开(公告)日：2021-03-18

    申请号：US16813317

    申请日：2020-03-09

    Applicant: Silicon Storage Technology, Inc.

    Inventor： XIAOZHOU QIAN ,  XIAO YAN PI ,  VIPIN TIWARI

    IPC: G11C16/14 ,  G11C16/28 ,  G11C7/10

    Abstract: A memory device that includes a memory array having pluralities of non-volatile memory cells, a plurality of index memory cells each associated with a different one of the pluralities of the non-volatile memory cells, and a controller. The controller is configured to erase the pluralities of non-volatile memory cells, set each of the index memory cells to a first state, and program first data into the memory array by reading the plurality of index memory cells and determining that a first one of the index memory cells is in the first state, programming the first data into the plurality of the non-volatile memory cells associated with the first one of the index memory cells, and setting the first one of the index memory cells to a second state different from the first state.

    Method of making split gate non-volatile flash memory cell
    414.
    发明授权
    Method of making split gate non-volatile flash memory cell 有权

    公开(公告)号：US10833179B2

    公开(公告)日：2020-11-10

    申请号：US16576389

    申请日：2019-09-19

    Applicant: Silicon Storage Technology, Inc.

    Inventor： Chunming Wang ,  Leo Xing ,  Andy Liu ,  Melvin Diao ,  Xian Liu ,  Nhan Do

    IPC: H01L27/11521 ,  H01L27/11531 ,  H01L29/66 ,  H01L21/3213 ,  H01L27/11536 ,  H01L29/423 ,  H01L49/02

    Abstract: A method of forming a non-volatile memory cell on a substrate having memory cell and logic circuit regions by forming a pair of conductive floating gates in the memory cell region, forming a first source region in the substrate between the pair of floating gates, forming a polysilicon layer in both regions, forming an oxide layer over the polysilicon layer in the logic circuit region, performing a chemical-mechanical polish of the polysilicon layer in the memory cell area leaving a first block of the polysilicon layer between the floating gates that is separated from remaining portions of the polysilicon layer, and selectively etching portions of the polysilicon layer to result in: second and third blocks of the polysilicon layer disposed in outer regions of the memory cell area, and a fourth block of the polysilicon layer in the logic circuit region.

    Method of programming a split-gate flash memory cell with erase gate
    419.
    发明授权
    Method of programming a split-gate flash memory cell with erase gate 有权

    公开(公告)号：US10714489B2

    公开(公告)日：2020-07-14

    申请号：US16209515

    申请日：2018-12-04

    Applicant: Silicon Storage Technology, Inc.

    Inventor： Yuri Tkachev ,  Alexander Kotov ,  Nhan Do

    IPC: H01L29/788 ,  H01L27/11521 ,  G11C16/04

    Abstract: A memory device with a memory cell and control circuitry. The memory cell includes source and drain regions formed in a semiconductor substrate, with a channel region extending there between. A floating gate is disposed over a first portion of the channel region for controlling its conductivity. A select gate is disposed over a second portion of the channel region for controlling its conductivity. A control gate is disposed over the floating gate. An erase gate is disposed over the source region and adjacent to the floating gate. The control circuitry is configured to perform a program operation by applying a negative voltage to the erase gate for causing electrons to tunnel from the erase gate to the floating gate, and perform an erase operation by applying a positive voltage to the erase gate for causing electrons to tunnel from the floating gate to the erase gate.

    System and method for minimizing floating gate to floating gate coupling effects during programming in flash memory
    420.
    发明授权
    System and method for minimizing floating gate to floating gate coupling effects during programming in flash memory 有权

    公开(公告)号：US10699787B2

    公开(公告)日：2020-06-30

    申请号：US16783286

    申请日：2020-02-06

    Applicant: Silicon Storage Technology, Inc.

    Inventor： Vipin Tiwari ,  Nhan Do ,  Hieu Van Tran

    IPC: G11C16/10 ,  G11C11/56 ,  G11C16/04 ,  H01L29/788 ,  H01L29/423

    Abstract: An improved programming technique for non-volatile memory cell arrays, in which memory cells to be programmed with higher programming values are programmed first, and memory cells to be programmed with lower programming values are programmed second. The technique reduces or eliminates the number of previously programmed cells from being adversely incrementally programmed by an adjacent cell being programmed to higher program levels, and reduces the magnitude of adverse incremental programming for most of the memory cells, which is caused by floating gate to floating gate coupling. The memory device includes an array of non-volatile memory cells and a controller configured to identify programming values associated with incoming data, and perform a programming operation in which the incoming data is programmed into at least some of the non-volatile memory cells in a timing order of descending value of the programming values.

Patent Agency Ranking