公开(公告)号：US07646021B2

公开(公告)日：2010-01-12

申请号：US12402480

申请日：2009-03-11

Applicant: Yeong-Feng Wang ,  Chih-Jui Pan ,  Liang-Bin Yu

Inventor： Yeong-Feng Wang ,  Chih-Jui Pan ,  Liang-Bin Yu

IPC: H01L29/04

CPC classification number: H01L27/124 ,  G02F1/136213 ,  H01L27/1255 ,  H01L29/78642

Abstract: A TFT array substrate includes a substrate, a patterned first metallic layer, a patterned stack layer, a patterned dielectric layer, a patterned transparent conductive layer, and a patterned third metallic layer. Elements of each TFT in the TFT array substrate are arranged vertically, so that the TFT array substrate has relatively small fabrication area and is operable with a high conducting current. Further, the storage capacitance can be enhanced by enclosing or sandwiching the second metallic layer with the common lines and the transparent electrodes. In such a way, pixel flashing caused by those coupled signals can be reduced, thus promoting displaying quality thereof.

Abstract translation: TFT阵列基板包括基板，图案化第一金属层，图案化叠层，图案化电介质层，图案化透明导电层和图案化的第三金属层。 TFT阵列基板中的每个TFT的元件被垂直布置，使得TFT阵列基板具有相对较小的制造面积并且可以以高导电电流工作。 此外，可以通过用公共线和透明电极包围或夹持第二金属层来增强存储电容。 以这种方式，可以减少由这些耦合信号引起的像素闪烁，从而提高其显示质量。

公开(公告)号：US20090231706A1

公开(公告)日：2009-09-17

申请号：US12473678

申请日：2009-05-28

Applicant: Pin-Chen CHEN ,  Hui-Lung Kuo ,  Chih-Ho Chiu ,  Liang-Bin Yu

Inventor： Pin-Chen CHEN ,  Hui-Lung Kuo ,  Chih-Ho Chiu ,  Liang-Bin Yu

IPC: G02B5/30 ,  B29D11/00

CPC classification number: G02B5/203 ,  G02B5/1809 ,  G02F1/133516 ,  G02F1/133533 ,  Y10T428/1041

Abstract: A color filter having a bi-layer metal grating is formed by nanoimprint lithography. Nanoimprint lithography, a low cost technology, includes two alternatives, i.e., hot-embossing nanoimprint lithography and UV-curable nanoimprint lithography. Manufacture steps includes providing a substrate with a polymer material layer disposed thereon. A plurality of lands and grooves are formed in the polymer material layer, and a first metal layer and a second metal layer are disposed on the surfaces of the lands and grooves, respectively. Finally, a color filter having a bi-layer metal grating is obtained.

Abstract translation: 具有双层金属光栅的滤色器通过纳米压印光刻形成。 低成本技术的纳米压印光刻技术包括两种替代方案，即热压印纳米压印光刻和UV可固化纳米压印光刻。 制造步骤包括提供其上设置有聚合物材料层的基底。 在聚合物材料层中形成多个焊盘和沟槽，并且第一金属层和第二金属层分别设置在焊盘和焊盘的表面上。 最后，获得具有双层金属光栅的滤色器。

公开(公告)号：US07541267B1

公开(公告)日：2009-06-02

申请号：US11765611

申请日：2007-06-20

Applicant: Haihong Wang ,  Shibly S. Ahmed ,  Ming-Ren Lin ,  Bin Yu

Inventor： Haihong Wang ,  Shibly S. Ahmed ,  Ming-Ren Lin ,  Bin Yu

IPC: H01L21/28

CPC classification number: H01L29/785 ,  H01L29/42392 ,  H01L29/66795 ,  H01L29/7842

Abstract: A method includes forming a first rectangular mesa from a layer of semiconducting material and forming a first dielectric layer around the first mesa. The method further includes forming a first rectangular mask over a first portion of the first mesa leaving an exposed second portion of the first mesa and etching the exposed second portion of the first mesa to produce a reversed T-shaped fin from the first mesa.

Abstract translation: 一种方法包括从半导体材料层形成第一矩形台面并在第一台面周围形成第一介电层。 该方法还包括在第一台面的第一部分上形成第一矩形掩模，离开第一台面的暴露的第二部分并蚀刻第一台面的暴露的第二部分以从第一台面产生反向的T形翅片。

公开(公告)号：US07351638B1

公开(公告)日：2008-04-01

申请号：US10021782

申请日：2001-12-18

Applicant: Cyrus E. Tabery ,  Eric N. Paton ,  Bin Yu ,  Qi Xiang ,  Robert B. Ogle

Inventor： Cyrus E. Tabery ,  Eric N. Paton ,  Bin Yu ,  Qi Xiang ,  Robert B. Ogle

IPC: H01L21/336

CPC classification number: H01L21/268 ,  H01L21/26513 ,  H01L29/6659

Abstract: A method of manufacturing a semiconductor device includes forming a gate electrode over a substrate, implanting dopants into the substrate and activating the dopants using laser thermal annealing. During annealing, the laser and substrate are moved relative to one another, and the movement of the laser and the substrate relative to one another does not pause between and during activating one portion of the source/drain regions and activating another portion of the source/drain regions. Each pulse from the laser can respectively irradiate different portions of the source/drain regions, and a spot area of the laser is less than 50 millimeter2.

Abstract translation: 一种制造半导体器件的方法包括在衬底上形成栅电极，将掺杂剂注入到衬底中并使用激光热退火激活掺杂剂。 在退火期间，激光器和衬底相对于彼此移动，并且激光器和衬底相对于彼此的运动在激活源极/漏极区域的一部分之间和在激活源极/漏极区域的另一部分之间不间断， 漏区。 来自激光器的每个脉冲可以分别照射源极/漏极区域的不同部分，并且激光器的斑点面积小于50毫米2。

公开(公告)号：US20080039081A1

公开(公告)日：2008-02-14

申请号：US11857146

申请日：2007-09-18

Applicant: Chunyan MA ,  Bin YU

Inventor： Chunyan MA ,  Bin YU

IPC: H04Q7/20

CPC classification number: H04L61/1588 ,  H04L29/12188 ,  H04L63/08 ,  H04L65/1006 ,  H04L65/1016 ,  H04L65/1043

Abstract: A method for implementing an IP Multimedia Subsystem (IMS) registration, includes: a Home Subscriber Server (HSS) recording a current registration state of a User Equipment (UE) in response to receiving a Multimedia Authentication Request (MAR) initiated by a Service Call Session Control Function (S-CSCF) selected for the UE when a first Register request is sent by the UE; in response to receiving a second Register request initiated by an Interrogating Call Session Control Function (I-CSCF), the HSS sends the S-CSCF Name to the I-CSCF when the current registration state of the UE is an assigned S-CSCF state. By the scheme, a same S-CSCF is ensured to be used in the two User Authentication Request/User Authentication Answer (UAR/UAA) procedures of the initial IMS registration procedure, and the initial IMS registration of the UE is implemented successfully.

Abstract translation: 一种用于实现IP多媒体子系统（IMS）注册的方法，包括：响应于接收到由服务呼叫发起的多媒体认证请求（MAR）来记录用户设备（UE）的当前注册状态的归属订户服务器（HSS） 当UE发送第一个Register请求时为UE选择的会话控制功能（S-CSCF）; 响应于接收到由询问呼叫会话控制功能（I-CSCF）发起的第二寄存器请求，当UE的当前注册状态是分配的S-CSCF状态时，HSS向I-CSCF发送S-CSCF名称 。 通过该方案，确保在初始IMS注册过程的两个用户认证请求/用户认证应答（UAR / UAA）过程中使用相同的S-CSCF，并且成功实现了UE的初始IMS注册。

公开(公告)号：US07298007B1

公开(公告)日：2007-11-20

申请号：US11171399

申请日：2005-07-01

Applicant: Wiley Eugene Hill ,  Bin Yu

Inventor： Wiley Eugene Hill ,  Bin Yu

IPC: H01L29/76

CPC classification number: H01L27/1108 ,  H01L21/845 ,  H01L27/11 ,  H01L27/1211 ,  H01L29/66803 ,  H01L29/785 ,  Y10S257/903 ,  Y10S438/944

Abstract: A memory device includes multiple fins formed adjacent to one another, a source region, a drain region, a gate, a wordline, and a bitline contact. At least one of the multiple fins is doped with a first type of impurities and at least one other one of the fins is doped with a second type of impurities. The source region is formed at one end of each of the fins and the drain region is formed at an opposite end of each of the fins. The gate is formed over two of the multiple fins, the wordline is formed over each of the multiple fins, and a bitline contact is formed adjacent at least one of the multiple fins.

Abstract translation: 存储器件包括彼此相邻形成的多个鳍，源极区，漏极区，栅极，字线和位线接触。 多个翅片中的至少一个被掺杂有第一类型的杂质，并且至少另外一个翅片掺杂有第二类型的杂质。 源区域形成在每个散热片的一端，并且漏极区域形成在每个散热片的相对端。 栅极形成在多个散热片的两个之上，字线形成在多个散热片的每一个上，并且与多个散热片中的至少一个相邻地形成有位线接触。

公开(公告)号：US07262104B1

公开(公告)日：2007-08-28

申请号：US10857931

申请日：2004-06-02

Applicant: Haihong Wang ,  Shibly S. Ahmed ,  Bin Yu

Inventor： Haihong Wang ,  Shibly S. Ahmed ,  Bin Yu

IPC: H01L21/336

CPC classification number: H01L29/785 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/66795

Abstract: Multiple semiconductor devices are formed with different threshold voltages. According to one exemplary implementation, first and second semiconductor devices are formed and doped differently, resulting in different threshold voltages for the first and second semiconductor devices.

Abstract translation: 形成具有不同阈值电压的多个半导体器件。 根据一个示例性实施例，第一和第二半导体器件被形成和掺杂不同，导致第一和第二半导体器件的不同阈值电压。

公开(公告)号：US07259425B2

公开(公告)日：2007-08-21

申请号：US10348911

申请日：2003-01-23

Applicant: Judy Xilin An ,  Haihong Wang ,  Bin Yu

Inventor： Judy Xilin An ,  Haihong Wang ,  Bin Yu

IPC: H01L29/72

CPC classification number: H01L29/785 ,  H01L29/42384 ,  H01L29/66545 ,  H01L29/66795

Abstract: A triple gate metal-oxide semiconductor field-effect transistor (MOSFET) includes a fin structure, a first gate formed adjacent a first side of the fin structure, a second gate formed adjacent a second side of the fin structure opposite the first side, and a top gate formed on top of the fin structure. A gate around MOSFET includes multiple fins, a first sidewall gate structure formed adjacent one of the fins, a second sidewall gate structure formed adjacent another one of the fins, a top gate structure formed on one or more of the fins, and a bottom gate structure formed under one or more of the fins.

Abstract translation: 三栅极金属氧化物半导体场效应晶体管（MOSFET）包括翅片结构，邻近翅片结构的第一侧形成的第一栅极，与第一侧相对的翅片结构的第二侧附近形成的第二栅极，以及 形成在鳍结构顶部的顶门。 MOSFET周围的栅极包括多个散热片，邻近其中一个翅片形成的第一侧壁栅极结构，邻近另一个鳍片形成的第二侧壁栅极结构，形成在一个或多个翅片上的顶部栅极结构，以及底部栅极 在一个或多个翅片下形成的结构。

公开(公告)号：US07256455B2

公开(公告)日：2007-08-14

申请号：US10720166

申请日：2003-11-25

Applicant: Shibly S. Ahmed ,  Haihong Wang ,  Bin Yu

Inventor： Shibly S. Ahmed ,  Haihong Wang ,  Bin Yu

IPC: H01L27/12 ,  H01L29/786 ,  H01L29/76

CPC classification number: H01L29/785 ,  H01L29/42384 ,  H01L29/66545 ,  H01L29/66795

Abstract: A semiconductor device may include a substrate, an insulating layer formed on the substrate and a conductive fin formed on the insulating layer. The conductive fin may include a number of side surfaces and a top surface. The semiconductor device may also include a source region formed on the insulating layer adjacent a first end of the conductive fin and a drain region formed on the insulating layer adjacent a second end of the conductive fin. The semiconductor device may further include a metal gate formed on the insulating layer adjacent the conductive fin in a channel region of the semiconductor device.

Abstract translation: 半导体器件可以包括衬底，形成在衬底上的绝缘层和形成在绝缘层上的导电鳍。 导电翅片可以包括多个侧表面和顶表面。 半导体器件还可以包括形成在与导电鳍片的第一端相邻的绝缘层上的源极区域和形成在与导电鳍片的第二端相邻的绝缘层上的漏极区域。 半导体器件还可以包括在半导体器件的沟道区域中形成在与绝缘层相邻的导电鳍片上的金属栅极。

公开(公告)号：US20070141791A1

公开(公告)日：2007-06-21

申请号：US11677404

申请日：2007-02-21

Applicant: Ming-Ren Lin ,  Bin Yu

Inventor： Ming-Ren Lin ,  Bin Yu

IPC: H01L21/336

CPC classification number: H01L29/785 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/66795 ,  H01L29/78687

Abstract: A semiconductor device includes a substrate and an insulating layer on the substrate. The semiconductor device also includes a fin structure formed on the insulating layer, where the fin structure includes first and second side surfaces, a dielectric layer formed on the first and second side surfaces of the fin structure, a first gate electrode formed adjacent the dielectric layer on the first side surface of the fin structure, a second gate electrode formed adjacent the dielectric layer on the second side surface of the fin structure, and a doped structure formed on an upper surface of the fin structure in the channel region of the semiconductor device.

Abstract translation: 半导体器件包括衬底和衬底上的绝缘层。 半导体器件还包括形成在绝缘层上的翅片结构，其中鳍结构包括第一和第二侧表面，形成在鳍结构的第一和第二侧表面上的电介质层，形成在电介质层附近的第一栅电极 在翅片结构的第一侧表面上形成与鳍结构的第二侧表面上的电介质层相邻的第二栅电极，以及在半导体器件的沟道区中形成在鳍结构的上表面上的掺杂结构 。