公开(公告)号：US5563534A

公开(公告)日：1996-10-08

申请号：US240024

申请日：1994-05-09

Applicant: Domenico Rossi ,  Masayuki Tateoka

Inventor： Domenico Rossi ,  Masayuki Tateoka

IPC: G01R19/165 ,  H03K3/0233 ,  H03K5/08 ,  H03K5/153

CPC classification number: H03K3/02337

Abstract: A hysteresis comparator circuit working with a low voltage supply and of a type which includes a composite structure incorporating first and second differential cells respectively comprised of an npn bipolar transistor pair with common emitters, on the one side, and a pair of pnp bipolar transistor pair with common emitters, on the other, such cells being coupled together through the bases of the respective transistors. The circuit includes at least one pair of variable current sources associated with each cell and tied operatively to the voltage value present on the comparator output; in addition, a voltage divider is connected between each interconnection of the bases of the transistors forming the cells.

Abstract translation: 一种工作于低电压电源的滞环比较器电路，以及一种包括一个复合结构的结构，该复合结构包含第一和第二微分电池，该第一和第二微分电池分别包括一侧的npn双极型晶体管对和一个共同的发射极，以及一对pnp双极晶体管对 与共同的发射极，另一方面，这些电池通过相应晶体管的基极耦合在一起。 该电路包括与每个电池相关联的至少一对可变电流源，并且可操作地连接到比较器输出端上存在的电压值; 此外，在形成电池的晶体管的基极的每个互连之间连接有分压器。

公开(公告)号：US5559743A

公开(公告)日：1996-09-24

申请号：US412550

申请日：1995-03-29

Applicant: Luigi Pascucci ,  Marcello Carrera ,  Marco Defendi

Inventor： Luigi Pascucci ,  Marcello Carrera ,  Marco Defendi

IPC: G11C17/00 ,  G11C5/02 ,  G11C16/06 ,  G11C29/00 ,  G11C29/04 ,  H01L21/82 ,  H01L21/822 ,  H01L27/04 ,  H01L27/10 ,  G11C7/00

CPC classification number: G11C29/80 ,  G11C5/025

Abstract: Redundancy circuitry layout for a semiconductor memory device comprises an array of programmable non-volatile memory elements for storing the addresses of detective bit lines and word lines which must be functionally replaced respectively by redundancy bit lines and word lines. The redundancy circuitry layout is divided into identical layout strips which are perpendicular to the array of memory elements and which each comprise first and a second strip sides located at opposite sides of the array of memory elements, the first strip side containing at least one programmable non-volatile memory register of a first plurality for the selection or redundancy bit lines and being crossed by a column address signal bus running parallel to the array or memory elements, the second strip side containing one programmable non-volatile memory register of a second plurality for the selection or redundancy word lines and being crossed by a row address signal bus running parallel to the array of memory elements.

Abstract translation: 用于半导体存储器件的冗余电路布局包括用于存储必须由冗余位线和字线分别功能地替换的检测位线和字线的地址的可编程非易失性存储器元件阵列。 冗余电路布局被分成与存储元件阵列垂直的相同的布局条，并且每个布局条包括位于存储元件阵列的相对侧的第一和第二条边，第一条边包含至少一个可编程非 用于选择或冗余位线的第一多个的非易失性存储器寄存器，并且被与阵列或存储器元件并行运行的列地址信号总线交叉，第二条侧包含第二多个的可编程非易失性存储寄存器， 选择或冗余字线并且被与存储器元件阵列平行运行的行地址信号总线交叉。

公开(公告)号：US5557236A

公开(公告)日：1996-09-17

申请号：US308708

申请日：1994-09-19

Applicant: Marco Monti

Inventor： Marco Monti

IPC: G06F15/78 ,  H03K17/687 ,  H03K19/0175 ,  H03K19/173 ,  H01L25/00

CPC classification number: H03K19/1732

Abstract: An integrated circuit has at least one input terminal and at least one output terminal, respectively, for receiving and transmitting digital and/or analog signals, being associated with discrete circuit portions of the integrated circuit which implement different logic functions. Advantageously, such terminals are coincident with a single pin, and an electronic circuit is arranged within the integrated circuit to detect the logic state of the pin.

Abstract translation: 集成电路分别具有用于接收和发送数字和/或模拟信号的至少一个输入端子和至少一个输出端子，其与实现不同逻辑功能的集成电路的分立电路部分相关联。 有利地，这种端子与单个引脚重合，并且电子电路布置在集成电路内以检测引脚的逻辑状态。

公开(公告)号：US5555168A

公开(公告)日：1996-09-10

申请号：US98651

申请日：1993-07-28

Applicant: Bruno Ferrario

Inventor： Bruno Ferrario

IPC: H02M3/155 ,  H02M1/00 ,  H02M1/42 ,  H03K7/06 ,  H02M7/155

CPC classification number: H02M1/4225 ,  H03K7/06 ,  Y02B70/126

Abstract: A switching power supply in which the oscillation frequency is dynamically controlled to have an instantaneous frequency value which is reduced when the power line waveform is near its peaks. This is preferably accomplished by a divider circuit, which provides an output current proportional to the ratio between the instantaneous value of the rectified voltage and the long-term-averaged value of that voltage. This output current is fed into a ramp generator, to dynamically shift the frequency of the ramp generator as the output current changes. This circuit is indifferent to power line voltage and frequency (over a fairly wide range), and therefore may be used in different countries having different power standards.

Abstract translation: 一种开关电源，其中振荡频率被动态地控制为具有在电力线波形接近其峰值时减小的瞬时频率值。 这优选地通过分频器电路实现，该分频器电路提供与整流电压的瞬时值与该电压的长期平均值之比成比例的输出电流。 该输出电流被馈送到斜坡发生器，以在输出电流变化时动态地移动斜坡发生器的频率。 该电路对电力线电压和频率（在相当宽的范围内）无动于衷，因此可用于具有不同功率标准的不同国家。

公开(公告)号：US5543633A

公开(公告)日：1996-08-06

申请号：US92717

申请日：1993-07-15

Applicant: Aldo Losavio ,  Giuseppe Crisenza ,  Giorgio De Santi

Inventor： Aldo Losavio ,  Giuseppe Crisenza ,  Giorgio De Santi

IPC: G01B7/34 ,  G01B21/30 ,  H01L21/66 ,  H01L23/58

CPC classification number: G01B21/30 ,  G01B7/345

Abstract: A method for measuring the degree of planarity in an integrated circuit includes depositing, onto a dielectric layer to be measured for planarity, a predetermined measure path of a conductive film and measuring the electric resistance of said measure path. The resistance of such a measure path is minimal where the surface on which it has been deposited is perfectly planar, and increases with the surface deviation from perfect planarity. An integrated circuit containing a measurement portion of conductive film and a reference portion of conductive film is described.

Abstract translation: 一种用于测量集成电路中的平面度的方法包括：将待测量的电介质层平坦化地沉积在导电膜的预定测量路径上并测量所述测量路径的电阻。 这种测量路径的电阻在其沉积的表面是完全平坦的时是最小的，并且随着与完美平面性的表面偏差而增加。 描述了包含导电膜的测量部分和导电膜的参考部分的集成电路。

公开(公告)号：US5532645A

公开(公告)日：1996-07-02

申请号：US328233

申请日：1994-10-24

Applicant: Mauro Fagnani ,  Bruno Ferrario ,  Paolo Sandri

Inventor： Mauro Fagnani ,  Bruno Ferrario ,  Paolo Sandri

IPC: H03F3/343 ,  H03F1/00 ,  H03F1/30 ,  H03F3/26

CPC classification number: H03F1/305

Abstract: A circuit for regulating the charging time of the output node of an amplifier at start up. The output node commonly comprises an external soft-start capacitor charged by a current delivered by a pull-up transistor of a push-pull output stage of the amplifier, through a decoupling diode that is functionally connected between the output node of the amplifier and a terminal of the external soft-start capacitor. The present application provides a current mirror feed back circuit capable of mirroring the charge current of the external soft-start capacitor onto the driving node of the pull-up transistor of the output stage of the amplifier. The regulating circuit permits use of an external capacitance of extremely small size. Upon the reaching of a fully charged condition by the external capacitor, the control circuit self-isolates and does not influence in any way the normal operation of the amplifier.

Abstract translation: 用于调节放大器输出节点在启动时的充电时间的电路。 输出节点通常包括由放大器的推挽输出级的上拉晶体管通过放大器的上拉输出级提供的电流充电的外部软启动电容器，该去耦二极管功能上连接在放大器的输出节点和 端子的外部软启动电容。 本申请提供了能够将外部软启动电容器的充电电流镜像到放大器的输出级的上拉晶体管的驱动节点上的电流镜反馈电路。 调节电路允许使用极小尺寸的外部电容。 当外部电容器达到完全充电状态时，控制电路自我隔离并且不会以任何方式影响放大器的正常工作。

公开(公告)号：US5530345A

公开(公告)日：1996-06-25

申请号：US129842

申请日：1993-09-30

Applicant: Bruno Murari ,  Sandro Storti ,  Flavio Villa

Inventor： Bruno Murari ,  Sandro Storti ,  Flavio Villa

IPC: H01L27/22 ,  G01D5/14 ,  H01L43/06 ,  G01R33/06

CPC classification number: G01D5/145 ,  H01L43/065

Abstract: For detecting the position of a magnetic element having a field component zeroing in at least one point in space, typically in a plane, a plurality of elementary Hall-effect sensors are integrated side by side and aligned in a direction perpendicular to the zeroing field component and to the current flowing through the elementary sensors. The elementary sensor generating a zero output voltage therefore indicates the zero position of the field component and consequently the position of the magnetic element with respect to the position sensor, so that The outputs of the elementary sensors provide a quantized numeric code indicating the position of the magnetic element.

Abstract translation: 为了检测在空间中的至少一个点（通常在平面中）具有场分量归零的磁性元件的位置，多个基本的霍尔效应传感器被并排并排并且在垂直于零点分量 以及流经基本传感器的电流。 因此，产生零输出电压的基本传感器指示场分量的零位，并因此表示磁元件相对于位置传感器的位置，使得基本传感器的输出提供表示位置传感器的位置的量化数字代码 磁性元件。

公开(公告)号：US5528184A

公开(公告)日：1996-06-18

申请号：US85207

申请日：1993-06-28

Applicant: Alberto Gola ,  Giona Fucili

Inventor： Alberto Gola ,  Giona Fucili

IPC: G06F1/24 ,  H03K17/00 ,  H03K17/22 ,  H03K5/153

CPC classification number: H03K17/223 ,  H03K2217/0036

Abstract: A power-on reset circuit which employs a supply voltage sensing branch for triggering a first inverter of a pair of cascaded inverters. The intrinsic static consumption of such a POR circuit is strongly reduced by employing a current generator, which is automatically forced to deliver a reduced current during the operation of the integrated circuit, for biasing two transistors functionally connected in said voltage sensing branch into a subthreshold operating condition.

Abstract translation: 一种上电复位电路，其采用电源电压感测支路来触发一对级联逆变器的第一反相器。 这种POR电路的固有静态消耗通过采用电流发生器而大大降低，该电流发生器在集成电路的操作期间被自动强制传递减小的电流，用于将功率上连接在所述电压感测分支中的两个晶体管偏压到次阈值操作 条件。

公开(公告)号：US5527728A

公开(公告)日：1996-06-18

申请号：US329309

申请日：1994-10-26

Applicant: Paolo Ghezzi ,  Federico Pio ,  Carlo Riva

Inventor： Paolo Ghezzi ,  Federico Pio ,  Carlo Riva

IPC: H01L21/8247 ,  H01L21/28 ,  H01L21/336 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC classification number: H01L29/66825 ,  H01L21/28273 ,  H01L29/7883 ,  H01L27/115 ,  Y10S438/911 ,  Y10S438/981

Abstract: A method for forming thin oxide portions in electrically erasable and programmable read-only memory cells, including the use of the enhanced oxidation effect and the lateral diffusion of heavy doping, for obtaining a tunnel portion whose dimensions are smaller than the resolution of the photolithographic method used.

Abstract translation: 一种用于在电可擦除和可编程只读存储器单元中形成薄氧化物部分的方法，包括使用增强的氧化效应和重掺杂的横向扩散，以获得其尺寸小于光刻方法的分辨率的隧道部分 用过的。

公开(公告)号：US5523632A

公开(公告)日：1996-06-04

申请号：US127816

申请日：1993-09-28

Applicant: Giordano Seragnoli

Inventor： Giordano Seragnoli

IPC: G05F1/56 ,  H02P8/16 ,  H03K17/64 ,  H03K17/695 ,  H01H36/00

CPC classification number: H03K17/64 ,  Y10T307/826

Abstract: A circuit device for recovering energy from an inductive load is connected to a protection circuit for protecting a driver circuit from a charge contained in the inductive load. The inductive load is connected between a power supply line at one end and the driver circuit and protection circuit at another end. The circuit device has a charge accumulator, preferably a capacitor, connected to the protection circuit for accumulating charge from the inductive load. A control circuit monitors the level of charge in the capacitor. A switch, connected between the capacitor and the power supply line, permits the charge accumulated in the capacitor to discharge into the power supply line. The control circuit controls the switch so as to permit the intermittent discharge of the inductive load: the switch is opened to permit charge from the inductive load to accumulate in the capacitor; and, the switch is closed to permit the capacitor to discharge the accumulated charge to the power supply line.

Abstract translation: 用于从感性负载恢复能量的电路装置连接到保护电路，用于保护驱动器电路免受包含在感性负载中的电荷。 感性负载连接在一端的电源线和另一端的驱动电路和保护电路之间。 电路装置具有连接到保护电路的电荷累加器，优选地是电容器，用于累积来自感性负载的电荷。 控制电路监视电容器的电荷电平。 连接在电容器和电源线之间的开关允许积聚在电容器中的电荷放电到电源线中。 控制电路控制开关以允许感性负载的间歇放电：开关断开以允许电感负载的电荷累积在电容器中; 并且开关闭合以允许电容器将累积的电荷放电到电源线。